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US 2002/0171491 A1Published application
Non-linear signal processor
AssigneeThomson Licensing
InventorDal Frank Griepentrog
Life of this patent
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Abstract
A signal processor which provides non-linear transfer functions provides a processor output and non-linear inflection points that are referenced to a common bias. The processor output and the non-linear inflection points each exhibit rejection to time variant common-mode variations.
Claims20
A non-linear processor, comprising:
- a processor (10) for amplifying a partially differential signal, said partially differential signal comprising a time-variant signal (12) and a common-mode bias (14), and for rejecting a time-variant common-mode signal imposed upon said partially differential signal;
- means (30) for establishing a threshold level (28) representative of said common-mode bias (14);
- means (32) for altering the gain of said processor in response to a predetermined relationship existing between said time-variant signal (12) and said threshold level (28);
- and
- means (30,32) for substantially preventing said time-variant common-mode signal from modifying said predetermined relationship.
2 more elements
A method for non-linearly processing signals, comprising the steps of:
- processing a partially differential signal comprising a time-variant signal (12) and a common-mode bias (14) for said partially differential signal, said processing to reject a time-variant common-mode signal imposed upon said partially differential signal;
- developing a threshold value (28) representative of said common-mode bias (14);
- altering non-linearly said processing of said partially differential signal in response to a predetermined relationship existing between said time-variant signal (12) and said threshold level (28);
- and
- preventing alterations of said predetermined relationship in response to said time-variant common-mode signal.
2 more elements
Apparatus for non-linearly amplifying electrical signals, comprising:
- A first input (14) to the base of a first transistor (16);
- a second input (12) to the base of a second transistor (18);
- a first resistor (22) interconnected between the emitters of said first (16) and said second (18) transistors;
- the collector of said first (16) transistor connected to a source of DC supply potential adequate to reverse bias the base to collector junction of said first transistor (16);
- the collector of said second (18) transistor connected through a second resistor (20) to a source of DC supply potential adequate to reverse bias the base to collector junction of said second transistor (18);
- an output terminal connected to said second transistor (18) collector at the junction of said second transistor (18) collector and one end of said second resistor (20);
- current sources (24,26) connected from each of the emitters of said first (16) and said second (18) transistors to a second source of DC supply potential;
- a first secondary gain setting resistor (34) connected from the emitter of said second transistor (18) to the emitter of a third transistor (36), the collector of said third transistor (36) connected to a collector DC supply potential adequate to reverse bias the base to collector junction of said third transistor (36);
- and
- the base of said third transistor (36) connected to a source of threshold potential (28).
7 more elements
Dependencies are inferred from the claim text.