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US 2002/0171459 A1Published application
Phase control digital frequency divider
AssigneeSTMicroelectronics S.r.l.
InventorAndrew Dellow
Life of this patent
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Abstract
A digital frequency divider includes phase control of the output signal in increments of whole or half cycles of the input frequency. Whole cycle phase control is achieved by varying (logically or physically) the tap off point of a shift register loaded with a bit pattern for appropriate division. Half cycle phase changes are achieved by a multiplexer selecting one of two signals every half cycle.
Claims30
A digital frequency divider for dividing a clock frequency and having a variable phase output, comprising:
- a shift register for storing a bit sequence chosen according to a division factor and operating under control of a clock signal at a first frequency;
- a tap off circuitry arranged to tap the shift register at one or more variable points and arranged to produce two or more signals representative of the bit sequence;
- a control logic circuitry having at least two inputs respectively arranged to receive the two or more signals representative of the bit sequence and arranged to provide at least two output signals;
- and a multiplexer arranged to receive the two output signals and to select one of the output signals in turn under control of the clock signal at the first frequency to thereby produce a clock output signal at a second frequency being a division of the first frequency;
- wherein the tap off circuitry and shift register are arranged such that the one or more tap off points of the shift register are variable in position along the bit sequence such that the clock output signal is variable in phase.
2 more elements
A frequency divider comprising:
- a first input clock having a first frequency;
- a storage register that stores a first bit sequence and a input receiving the first clock;
- a selection circuit having an input, an output, and a control, the input of the selection circuit receiving the first bit sequence, and the output providing a second bit sequence;
- a control register having an input and output, the input of the control register receiving the first clock, and the output providing a selection status to the control of the selection circuit to alter the first bits sequence, thereby selecting the second bit sequence;
- and
- a logic circuit having first, second, and third inputs and an output, the first input receiving an operation status, the second input receiving a direction status, the third input receiving the second bit sequence, and the output providing a second clock having a second frequency such that the second frequency is a fraction of the first frequency of the first clock.
3 more elements
A method of operation of a frequency divider comprising the steps of:
- providing a first clock of a first frequency having a positive and negative phase;
- selecting a bit sequence representative of a divisor value;
- loading a first storage register with the bit sequence;
- outputting the bit sequence from the first storage register at the first frequency, thereby providing an intermediate signal having a positive and negative phase;
- and
- altering the intermediate signal in relation to the positive or negative phase of the first clock to produce a second clock having a second frequency a fraction of the first frequency.
3 more elements
Dependencies are inferred from the claim text.