Compound structure for reduced contact resistance

A method of reducing contact resistance to a silicon-containing material, comprising:

• forming a first refractory metal material on the silicon-containing material, wherein the first refractory metal material is a conductive material containing a first refractory metal and a first impurity capable of forming a chemical bond with the first refractory metal, and wherein the first refractory metal material contains the first impurity at a level less than a stoichiometric level;
• forming a second refractory metal material on the first refractory metal material, wherein the second refractory metal material is a conductive material containing a second refractory metal and a second impurity capable of forming a chemical bond with the second refractory metal, and wherein the second refractory metal material has a lower affinity for the first and second impurities than does the first refractory metal material;
• and
• annealing to form a refractory metal silicide interface between the first refractory metal material and the silicon-containing material.

A method of reducing contact resistance to a silicon-containing material, comprising:

• forming a first refractory metal nitride layer on the silicon-containing material, wherein the first refractory metal nitride layer is an unsaturated refractory metal nitride material;
• forming a second refractory metal nitride layer on the first refractory metal nitride layer, wherein the second refractory metal nitride layer has a lower affinity for nitrogen than the first refractory metal nitride layer;
• and
• annealing to form a refractory metal silicide interface between the first refractory metal nitride layer and the silicon-containing material.

A method of reducing contact resistance to a silicon-containing material, comprising:

• forming an unsaturated titanium nitride layer on the silicon-containing material;
• forming a refractory metal nitride layer on the unsaturated titanium nitride layer;
• and
• annealing to form a titanium silicide interface between the unsaturated titanium nitride layer and the silicon-containing material.

A method of reducing contact resistance to a silicon-containing material, comprising:

• forming an unsaturated titanium nitride layer on the silicon-containing material;
• forming a saturated tungsten nitride layer on the unsaturated titanium nitride layer;
• and
• annealing to form a titanium silicide interface between the unsaturated titanium nitride layer and the silicon-containing material.

A method of reducing contact resistance to a silicon-containing material, comprising:

• forming a titanium nitride layer on the silicon-containing material, wherein the titanium nitride layer is formed by reactive sputtering from a titanium target in a nitrogen-containing ambient to produce an unsaturated titanium nitride material of the form TiNx where x is in the range of approximately 0.2 to approximately 0.8;
• forming a refractory metal nitride layer on the titanium nitride layer, wherein the refractory metal nitride layer has a lower affinity for nitrogen than the titanium nitride layer;
• and
• annealing to form a refractory metal silicide interface between the titanium nitride layer and the silicon-containing material.

A method of reducing contact resistance to a silicon-containing material, comprising:

• forming a titanium nitride layer on the silicon-containing material, wherein the titanium nitride layer is formed by reactive sputtering from a titanium target in a nitrogen-containing ambient to produce an unsaturated titanium nitride material having a bulk resistivity within 15% of a maximum unsaturated bulk resistivity;
• forming a refractory metal nitride layer on the titanium nitride layer, wherein the refractory metal nitride layer has a lower affinity for nitrogen than the titanium nitride layer;
• and
• annealing to form a refractory metal silicide interface between the titanium nitride layer and the silicon-containing material.

A method of reducing contact resistance to a silicon-containing material, comprising:

• forming an unsaturated titanium nitride layer on the silicon-containing material using an ionized metal plasma process;
• forming a tungsten nitride layer on the unsaturated titanium nitride layer;
• and
• annealing to form a refractory metal silicide interface between the unsaturated titanium nitride layer and the silicon-containing material.

A method of reducing contact resistance to a silicon-containing material, comprising:

• forming a nitrogen-acceptor refractory metal nitride layer on the silicon-containing material;
• forming a nitrogen-donor refractory metal nitride layer on the nitrogen-acceptor refractory metal nitride layer;
• and
• annealing to form a refractory metal silicide interface at a lower portion of the nitrogen-acceptor refractory metal nitride layer.

A method of forming a bit-line stack in a memory device, the method comprising:

• forming a conductively-doped polysilicon contact plug coupled to a source/drain region of an access transistor of a memory cell in the memory device;
• forming an unsaturated titanium nitride layer on the polysilicon contact plug;
• forming a saturated tungsten nitride layer on the titanium nitride layer;
• annealing to form a titanium silicide interface between the unsaturated titanium nitride layer and the polysilicon contact plug;
• and
• forming a tungsten bit line coupled to the saturated tungsten nitride layer.

A method of forming a bit-line stack in a memory device, the method comprising:

• forming a conductively-doped polysilicon contact plug coupled to a source/drain region of an access transistor of a memory cell in the memory device;
• forming a titanium nitride layer on the polysilicon contact plug, wherein the titanium nitride layer is formed by reactive sputtering from a titanium target in a nitrogen-containing ambient to produce an unsaturated titanium nitride material of the form TiNx where x is in the range of approximately 0.2 to approximately 0.8;
• forming a tungsten nitride layer on the titanium nitride layer, wherein the tungsten nitride layer has a lower affinity for nitrogen than the titanium nitride layer;
• annealing to form a titanium silicide interface between the titanium nitride layer and the polysilicon contact plug;
• and
• forming a tungsten bit line coupled to the tungsten nitride layer.

A method of forming a bit-line stack in a memory device, the method comprising:

• forming a titanium nitride layer on a silicon-containing source/drain region of an access transistor of a memory cell in the memory device, wherein the titanium nitride layer is formed by reactive sputtering from a titanium target in a nitrogen-containing ambient to produce an unsaturated titanium nitride material of the form TiNx where x is in the range of approximately 0.2 to approximately 0.8;
• forming a tungsten nitride layer on the titanium nitride layer, wherein the tungsten nitride layer has a lower affinity for nitrogen than the titanium nitride layer;
• annealing to form a titanium silicide interface between the titanium nitride layer and the source/drain region;
• and
• forming a tungsten bit line coupled to the tungsten nitride layer.

A method of forming a bit-line stack in a memory device, the method comprising:

• forming a conductively-doped polysilicon contact plug coupled to a source/drain region of an access transistor of a memory cell in the memory device;
• forming a titanium nitride layer on the polysilicon contact plug, wherein the titanium nitride layer is formed by reactive sputtering from a titanium target in a nitrogen-containing ambient to produce an unsaturated titanium nitride material having a bulk resistivity within 15% of a maximum unsaturated bulk resistivity;
• forming a tungsten nitride layer on the titanium nitride layer, wherein the tungsten nitride layer has a lower affinity for nitrogen than the titanium nitride layer;
• annealing to form a titanium silicide interface between the titanium nitride layer and the polysilicon contact plug;
• and
• forming a tungsten bit line coupled to the tungsten nitride layer.

A bit-line contact, comprising:

• a first refractory metal nitride layer overlying a silicon-containing material;
• a refractory metal silicide interface between the first refractory metal nitride layer and the silicon-containing material, wherein the refractory metal silicide interface is limited to a lower portion of the first refractory metal nitride layer;
• and
• a second refractory metal nitride layer overlying the first refractory metal nitride layer.

A bit-line contact, comprising:

• a first refractory metal nitride layer adjoining a silicon-containing contact plug;
• and
• a second refractory metal nitride layer overlying the first refractory metal nitride layer;
• wherein the first refractory metal nitride layer is an unsaturated refractory metal nitride material;
• and
• wherein the first refractory metal nitride layer has a higher affinity for nitrogen than the second refractory metal nitride layer.

A bit-line contact, comprising:

• a conductively-doped polysilicon contact plug;
• an unsaturated titanium nitride layer overlying the conductively-doped polysilicon contact plug;
• and
• a tungsten nitride layer overlying the unsaturated titanium nitride layer.

A bit-line contact, comprising:

• an unsaturated titanium nitride layer adjoining a silicon-containing material, wherein the silicon-containing material is selected from the group consisting of a conductively-doped polysilicon contact plug and a conductively-doped source/drain region;
• and
• a tungsten nitride layer overlying the unsaturated titanium nitride layer and having a lower affinity for nitrogen than the titanium nitride layer;
• wherein the unsaturated titanium nitride layer has a bulk resistivity within 15% of a maximum unsaturated bulk resistivity.

A bit-line stack, comprising:

• a conductively-doped polysilicon contact plug;
• an unsaturated titanium nitride layer overlying the conductively-doped polysilicon contact plug;
• a titanium silicide interface between the polysilicon contact plug and the unsaturated titanium nitride layer;
• a tungsten nitride layer overlying the unsaturated titanium nitride layer;
• and
• a tungsten layer overlying the tungsten nitride layer.

A bit-line stack, comprising:

• an unsaturated titanium nitride layer adjoining a silicon-containing material and having a titanium silicide interface formed therebetween, wherein the silicon-containing material is selected from the group consisting of a conductively-doped polysilicon contact plug and a conductively-doped source/drain region;
• a tungsten nitride layer overlying the unsaturated titanium nitride layer and having a lower affinity for nitrogen than the unsaturated titanium nitride layer;
• and
• a tungsten layer overlying the tungsten nitride layer;
• wherein the unsaturated titanium nitride layer has a bulk resistivity within 15% of a maximum unsaturated bulk resistivity.

A bit-line stack, comprising:

• a titanium nitride layer adjoining a silicon-containing material, wherein the titanium nitride layer is formed by reactive sputtering from a titanium target in a nitrogen-containing ambient to produce an unsaturated titanium nitride material of the form TiNx where x is in the range of approximately 0.2 to approximately 0.8;
• a tungsten nitride layer overlying the titanium nitride layer;
• and
• a tungsten layer overlying the tungsten nitride layer.

A word line for a memory cell, comprising:

• a gate dielectric layer;
• a gate polysilicon layer overlying the gate dielectric layer;
• an unsaturated titanium nitride layer overlying the gate polysilicon layer;
• a tungsten nitride layer overlying the unsaturated titanium nitride layer;
• and
• a gate conductor layer overlying the tungsten nitride layer.

A word line for a memory cell, comprising:

• a gate dielectric layer;
• a conductively-doped gate polysilicon layer overlying the gate dielectric layer;
• an unsaturated titanium nitride layer overlying the conductively-doped gate polysilicon layer;
• a tungsten nitride layer overlying the unsaturated titanium nitride layer and having a lower affinity for nitrogen than the unsaturated titanium nitride layer;
• and
• a gate conductor layer overlying the tungsten nitride layer;
• wherein the unsaturated titanium nitride layer has a bulk resistivity within 15% of a maximum unsaturated bulk resistivity.

A word line for a memory cell, comprising:

• a gate dielectric layer;
• a conductively-doped gate polysilicon layer overlying the gate dielectric layer;
• a titanium nitride layer overlying the gate polysilicon layer, wherein the titanium nitride layer is formed by a physical vapor deposition process to be an unsaturated titanium nitride material and to have a bulk resistivity within 15% of a maximum unsaturated bulk resistivity;
• a tungsten nitride layer overlying the titanium nitride layer;
• and
• a gate conductor layer overlying the tungsten nitride layer.

A word line for a memory cell, comprising:

• a gate dielectric layer;
• a conductively-doped gate polysilicon layer overlying the gate dielectric layer;
• a titanium nitride layer overlying the gate polysilicon layer, wherein the titanium nitride layer is formed by reactive sputtering from a titanium target in a nitrogen-containing ambient to produce an unsaturated titanium nitride material having a bulk resistivity within 15% of a maximum unsaturated bulk resistivity;
• a titanium silicide interface formed in a lower portion of the titanium nitride layer;
• a refractory metal nitride layer overlying the titanium nitride layer;
• and
• a gate conductor layer overlying the refractory metal nitride layer.

A word line for a memory cell, comprising:

• a gate dielectric layer;
• a conductively-doped gate polysilicon layer overlying the gate dielectric layer;
• a titanium nitride layer overlying the gate polysilicon layer, wherein the titanium nitride layer is formed by reactive sputtering from a titanium target in a nitrogen-containing ambient to produce an unsaturated titanium nitride material of the form TiNx where x is in the range of approximately 0.2 to approximately 0.8;
• a titanium silicide interface formed in a lower portion of the titanium nitride layer;
• a refractory metal nitride layer overlying the titanium nitride layer;
• and
• a gate conductor layer overlying the refractory metal nitride layer.

A word line for a memory cell, comprising:

• a gate dielectric layer;
• a conductively-doped gate polysilicon layer overlying the gate dielectric layer;
• a titanium nitride layer overlying the gate polysilicon layer, wherein the titanium nitride layer is of the form TiNx where x ranges from approximately 0.2 to approximately 0.8;
• a refractory metal nitride layer overlying the titanium nitride layer, wherein the refractory metal nitride layer has a lower affinity for nitrogen than the titanium nitride layer;
• and
• a gate conductor layer overlying the refractory metal nitride layer.

A memory cell, comprising:

• a gate stack overlying a silicon substrate;
• a first source/drain region and a second source/drain region in the silicon substrate on opposing sides of the gate stack;
• a capacitor having a bottom plate, a top plate and a dielectric layer interposed between the bottom plate and the top plate;
• a titanium nitride layer adjoining a silicon-containing material, wherein the titanium nitride layer is formed by reactive sputtering from a titanium target in a nitrogen-containing ambient to produce an unsaturated titanium nitride material having a bulk resistivity within 15% of a maximum unsaturated bulk resistivity, and wherein the silicon-containing material is selected from the group consisting of the first source/drain region and a silicon-containing contact plug adjoining the first source/drain region;
• a titanium silicide layer at the interface of the titanium nitride layer and the silicon-containing material;
• and
• a refractory metal nitride layer overlying the titanium nitride layer, wherein the refractory metal nitride layer is coupled to the bottom plate of the capacitor.

A memory cell, comprising:

• a gate stack overlying a silicon substrate;
• a first source/drain region and a second source/drain region in the silicon substrate on opposing sides of the gate stack;
• a capacitor having a bottom plate, a top plate and a dielectric layer interposed between the bottom plate and the top plate;
• a titanium nitride layer overlying a silicon-containing material, wherein the titanium nitride layer is formed by reactive sputtering from a titanium target in a nitrogen-containing ambient to produce an unsaturated titanium nitride material of the form TiNx where x is in the range of approximately 0.2 to approximately 0.8, and wherein the silicon-containing material is selected from the group consisting of the first source/drain region and a silicon-containing contact plug adjoining the first source/drain region;
• a titanium silicide interface between the titanium nitride layer and the silicon-containing material;
• and
• a refractory metal nitride layer overlying the titanium nitride layer, wherein the refractory metal nitride layer is coupled to the bottom plate of the capacitor.

A memory device, comprising:

• a plurality of bit lines, wherein each bit line contains tungsten;
• a plurality of word lines;
• and
• an array of memory cells, each memory cell located at an intersection of a bit line and a word line and each memory cell having a source/drain region coupled to a bit line through a bit-line contact;
• wherein at least one bit-line contact comprises:
• an unsaturated titanium nitride layer adjoining a silicon-containing material and having a titanium silicide interface formed therebetween, wherein the silicon-containing material is selected from the group consisting of a source/drain region associated with the bit-line contact and a conductively-doped polysilicon contact plug coupled to the source/drain region associated with the bit-line contact;
• and
• a tungsten nitride layer overlying the unsaturated titanium nitride layer and having a lower affinity for nitrogen than the unsaturated titanium nitride layer.

A memory device, comprising:

• a plurality of bit lines;
• a plurality of word lines;
• and
• an array of memory cells, each memory cell located at an intersection of a bit line and a word line;
• wherein at least one word line comprises:
• a gate dielectric layer;
• a gate polysilicon layer overlying the gate dielectric layer;
• an unsaturated titanium nitride layer overlying the gate polysilicon layer;
• a titanium silicide layer formed at an interface between the unsaturated titanium nitride layer and the gate polysilicon layer;
• a tungsten nitride layer overlying the unsaturated titanium nitride layer, wherein the tungsten nitride layer has a lower affinity for nitrogen than the unsaturated titanium nitride layer;
• and
• a tungsten layer overlying the tungsten nitride layer.

A memory device, comprising:

• a plurality of bit lines;
• a plurality of word lines;
• and
• an array of memory cells, each memory cell located at an intersection of a bit line and a word line;
• wherein at least one memory cell comprises:
• a gate stack overlying a silicon substrate;
• a first source/drain region and a second source/drain region in the silicon substrate on opposing sides of the gate stack;
• a capacitor having a bottom plate, a top plate and a dielectric layer interposed between the bottom plate and the top plate, wherein the bottom plate contains tungsten;
• an unsaturated titanium nitride layer adjoining a silicon-containing material, wherein the silicon-containing material is selected from the group consisting of the first source/drain region and a silicon-containing contact plug adjoining the first source/drain region;
• a titanium silicide layer formed at an interface between the unsaturated titanium nitride layer and the silicon-containing material;
• and
• a tungsten nitride layer overlying the unsaturated titanium nitride layer, wherein the tungsten nitride layer is coupled to the bottom plate of the capacitor and wherein the tungsten nitride layer has a lower affinity for nitrogen than the unsaturated titanium nitride layer.