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US 2002/0171098 A1Published application
Semiconductor device
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsShuji Nakaya, Mitsuaki Hayashi
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AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsShuji Nakaya, Mitsuaki Hayashi
Estimating the term…
On a semiconductor substrate surface, a drain diffusion layer, which is in common to two transistors that make up a memory cell pair, is formed and source diffusion layers, for each of the transistors, respectively, are formed so as to sandwich the drain diffusion layer from both sides, a bit line is formed from a lower wiring layer and is connected to the drain diffusion layer, a source line is formed from the uppermost wiring layer, and the writing of information is performed by making a contact hole exist or non-existent immediately below the source line arranged from the uppermost wiring layer, in other words, by connection or non-connection of the source diffusion layer with the source line. By this arrangement, the TAT can be shortened and, since the capacitance of the bit line is not increased, high-speed operation with a short precharge time and discharge time for the bit line can be realized and the consumption power can be lessened.
A semiconductor device comprising a drain diffusion layer, which is formed on a semiconductor substrate and is in common to first and second transistors that make up a memory cell pair, a source diffusion layer for said first transistor and a source diffusion layer for said second transistor, which are formed on said semiconductor substrate in a manner whereby they are spaced from the drain diffusion layer by predetermined intervals so as to sandwich the drain diffusion layer, a first word line, which is coupled to a gate electrode of said first transistor, a second word line, which is coupled to a gate electrode of said second transistor, a bit line, which is arranged from a first wiring layer above said semiconductor substrate and is connected to said drain diffusion layer, and a source line, which is arranged from a second wiring layer above said first wiring layer above said semiconductor substrate, wherein the writing of information is performed by connection or non-connection of the respective source diffusion layers of said first and second transistors with said source line.
Dependencies are inferred from the claim text.