Super-junction semiconductor device

A semiconductor device comprising:

• a semiconductor chip having a first major surface and a second major surface facing opposite to the first major surface;
• an active region on the side of the first major surface;
• a layer with low electrical resistance of a first conductivity type on the side of the second major surface;
• a vertical drain drift region between the active region and the layer with low electrical resistance;
• the vertical drain drift region comprising a first alternating conductivity type layer formed of first regions of the first conductivity type and second regions of a second conductivity type, the first regions and the second regions being laminated alternately;
• a very resistive region between the first major surface and the layer with low electrical resistance, the very resistive region surrounding the vertical drain drift region, the very resistive region being doped with an impurity of the first conductivity type and an impurity of the second conductivity type;
• a third region of the first conductivity type around the very resistive region;
• and
• a fourth region of the second conductivity type around the third region.

A method for manufacturing a semiconductor device comprising:

• forming a semiconductor chip having a first major surface and a second major surface facing opposite to the first major surface;
• forming an active region on the side of the first major surface;
• forming a layer with low electrical resistance of a first conductivity type on the side of the second major surface;
• forming a vertical drain drift region between the active region and the layer with low electrical resistance, the vertical drain drift region including a first alternating conductivity type layer formed of layer-shaped vertically-extending first regions of the first conductivity type and layer-shaped vertically-extending second regions of a second conductivity type, the first regions and the second regions being laminated alternately;
• forming a breakdown withstanding region between the first major surface and the layer with low electrical resistance, the breakdown withstanding region surrounding the vertical drain drift region, the breakdown withstanding region providing no current path in the ON-state of the semiconductor device, the breakdown withstanding region being depleted in the OFF-state of the semiconductor device, the breakdown withstanding region including a second alternating conductivity type layer formed of layer-shaped vertically-extending third regions of the first conductivity type and layer-shaped vertically-extending fourth regions of the second conductivity type, the third regions and the fourth regions being laminated alternately;
• forming a fifth region of the first conductivity type around the second alternating conductivity type layer;
• and
• forming a sixth region of the second conductivity type around the fifth region.

A method for manufacturing a semiconductor device comprising:

• forming a semiconductor chip having a first major surface and a second major surface facing opposite to the first major surface;
• forming an active region on the side of the first major surface;
• forming a layer with low electrical resistance of a first conductivity type on the side of the second major surface;
• forming a vertical drain drift region between the active region and the layer with low electrical resistance;
• the vertical drain drift region including a first alternating conductivity type layer formed of layer-shaped vertically-extending first regions of the first conductivity type and layer-shaped vertically-extending second regions of a second conductivity type, the first regions and the second regions being laminated alternately;
• forming a very resistive region between the first major surface and the layer with low electrical resistance, the very resistive region surrounding the vertical drain drift region, the very resistive region being doped with an impurity of the first conductivity type and an impurity of the second conductivity type;
• forming a third region of the first conductivity type around the very resistive region;
• and
• forming a fourth region of the second conductivity type around the third region.