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AssigneeInternational Business Machines Corporation
InventorsJack Oon Chu, Khalid EzzEldin Ismail, Steven John Koester, Bernd-Ulrich H. Klepser
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An integrated optoelectronic circuit and process for making is described incorporating a photodetector and a MODFET on a chip. The chip contains a single-crystal semiconductor substrate, a buffer layer of SiGe graded in composition, a relaxed SiGe layer, a quantum well layer, an undoped SiGe spacer layer and a doped SiGe supply layer. The photodetector may be a metal-semiconductor-metal (MSM) or a p-i-n device. The detector may be integrated with an nor p-type MODFET, or both in a CMOS configuration, and the MODFET can incorporate a Schottky or insulating gate. The invention overcomes the problem of producing Si-manufacturing-compatible monolithic high-speed optoelectronic circuits for 850 nm operation by using epixially-grown Si/SiGe heterostructure layers.
A semiconductor structure comprising a single crystal semiconductor substrate, a Sil-xGex buffer layer graded from x =0 to y where y is in the range from 0.1 to 1.0, a layer of relaxed Sil-yGey having a thickness in the range from 0.25 μm to 10 μm, a quantum well layer, an undoped Sil-yGey spacer layer, and a doped Sil-yGey supply layer, wherein said layer of relaxed Sil-yGey may function as the absorbing region of a photodetector, said quantum well layer may function as the conducting channel of a field-effect transistor, and said spacer layer may function to separate dopants in said supply layer from said conducting channel.
The semiconductor structure of claim I further including first and second spaced apart doped regions, one above the other, with a portion of said relaxed Sil-yGey layer there between to form a photodetector and an Ohmic contact to said respective first and second doped regions for applying a potential there between.
A semiconductor structure comprising a single crystal substrate, a Sil-xGex buffer layer graded from x =O to x =y, wherey is in the range from 0.1 to 0.9, a constant composition layer of relaxed Sil-yGey having a thickness in the range from 0.25 μm to 10 μm, a p-type doped Sil-wGew supply layer, where w <y, an undoped Sil-yGey spacer layer, a Sil-zGez quantum well layer, where z >y, and an additional undoped Sil-yGey spacer layer, wherein said constant composition layer of relaxed Sil-yGey may function as the absorbing region of a photodetector, and said Sil-zGez quantum well layer may function as the conducting channel of a field-effect transistor.
A semiconductor structure comprising a single crystal semiconductor substrate, a Sil-xGex buffer layer graded from x =O to y in the range from 0.1 to 0.9, followed by a plurality of layers forming a symmetrically-strained superlattice and consisting of alternating layers of Sil-wGew and Sil-zGez, where w <y <z, and having corresponding individual thicknesses such that the average Ge-composition of the layer is y, and having a total thickness in the range from 0.25 μm to 10 μm, and additionally a thin Sil-yGey layer, a quantum well layer, an undoped Sil-yGey spacer layer, and an n-type doped Sil-yGey supply layer, wherein said symmetric superlattice may function as the absorbing region of a photodetector, and said quantum well layer may function as the conducting channel of a field-effect transistor.
A semiconductor structure comprising a substrate selected from the group consisting of Si and SOI, a Sil-xGex buffer layer graded from x =O to x =y, where y is in the range from 0.1 to 1.0, a constant composition layer of relaxed Sil-yGey, of thickness 0.25 μm to 10 μm a thin Si surface layer, and a thin gate dielectric, wherein said constant composition layer of relaxed Sil-yGey acts as the absorbing region of a photodetector, and said Si surface layer acts as the conducting channel of a field-effect transistor.
A semiconductor structure comprising a single crystal semiconductor substrate, a Sil-xGex buffer layer graded from x =O to y where y is in the range from 0.1 to 0.9, a layer of relaxed Sil-yGey having a thickness in the range from 0.25 μm to 10 μm, an n-type doped Sil-yGey supply layer, a first undoped Sil-yGey layer, a second undoped Sil-yGey offset layer, a second quantum well layer, a third undoped Sil-yGey offset layer, an undoped Si layer, a gate dielectric and a gate electrode layer wherein said layer of relaxed Sil-yGey may function as the absorbing region of a photodetector, and said first quantum well layer may act as an electron channel for an n-MOSFET, and said second quantum well layer acts as a hole channel for a p-MOS FET.
A method for forming a semiconductor structure comprising the steps of:
A method of forming a semiconductor structure comprising the steps of:
A method for forming a semiconductor structure comprising the steps of:
A method for forming a semiconductor structure comprising the steps of:
A method for forming a semiconductor structure comprising the steps of forming a single crystal semiconductor substrate, forming a Sil-xGex buffer layer graded from x =O to y where y is in the range from 0.1 to 0.9, forming a layer of relaxed Sil-yGey having a thickness in the range from 0.25 μm to 10 μm, forming an n-type doped Sil-yGey supply layer, forming a first undoped Sil-yGey layer, forming a first quantum well layer which acts as an electron channel for an NMOS FET, forming a second undoped Sil-yGey offset layer, forming a second quantum well layer which acts as a hole channel for a PMOS FET, forming a third undoped Sil-yGey offset layer, forming an undoped Si layer, forming a gate dielectric and foming a gate electrode layer whereby NMOS FET's and PMOS FET's may be formed by forming the respective n-type and p-type drain and source regions.
Dependencies are inferred from the claim text.