Photomask and integrated circuit manufactured by automatically eliminating design rule violations during construction of a mask layout block

A photomask assembly, comprising:

• a pellicle assembly defined in part by a pellicle frame and a pellicle film attached thereto;
• and
• a photomask coupled to the pellicle assembly opposite from the pellicle film, the photomask including a patterned layer formed on a substrate, the patterned layer formed using a mask pattern file created by:
• analyzing a selected position of a polygon in a mask layout block;
• identifying a design rule violation in the mask layout block if the selected position is less than a design rule from a technology file;
• and
• automatically preventing the polygon from being placed in the mask layout block at the selected position if the design rule violation is identified.

An integrated circuit formed on a semiconductor wafer, comprising:

• a plurality of interconnect layers selected from the group consisting of n-well, p-well, diffusion, polysilicon and metal;
• and
• a plurality of contact layers operable to provide electrical connections between the interconnect layers;
• the interconnect and contact layers formed on a semiconductor wafer using a plurality of photomasks created by:
• analyzing a selected position of a polygon in a mask layout block;
• identifying a design rule violation in the mask layout block if the selected position is less than a design rule from a technology file;
• and
• automatically preventing the polygon from being placed in the mask layout block at the selected position if the design rule violation is identified.