High speed counters

Abstract

Implementing distributed reference counters in a multiprocessor computer ensures a fair allocation of memory to each of the CPUs and quads in the system. The distributed reference counter tracks the limits of the value in each CPU, each quad, a global value and the maximum cache count allowed while mitigating a cache overflow error. The cache count is dynamically varied based upon a desired level of cache value in a node and a CPU. By modifying the fields of the data structure of the distributed reference counter to accept 64 bit integers, both the cache and target values of the data structure may be combined into one 64 bit integer. The upper 32 bits represent the cache value and the lower 32 bits represent the target value. This modified data structure now allows for both the target and cache values to be atomically manipulated as a single quantity, thereby reducing the possibility of a cache overflow situation.

Dependencies are inferred from the claim text.