Memory interface protocol using two addressing modes and method of operation
AssigneeMotorola, Inc.
InventorCraig D. Shaw
Life of this patent
Estimating the term…
Abstract
A memory interface (15) and method of use implements a cache (14) bursting addressing technique which begins a read of main memory (16) in a wrap around mode before automatically switching into a linear addressing mode. The use of two modes which automatically change eliminates an access delay to the main memory when switching modes and optimizes system performance by providing a most critical word first in a first cache line fill and advancing to a sequential address following the first cache line. The sequential address has a higher probability of next use by the processor than any other address. The automatic mode change may be overridden by the memory interface.
Claims17
An integrated circuit, comprising:
- a cache comprising a plurality of cache lines, wherein the plurality of cache lines is characterized by comprising a plurality of words that are sequential and that begin with a boundary word at a line boundary;
- and
- interface means for initiating a fill of a first cache line in the plurality of cache lines including at least the boundary word of the first cache line in response to a request to provide a first selected word that is misaligned to the boundary within the first cache line by generating an address corresponding to the first selected word, a clock signal, and a load address signal and for initiating a fill of a second cache line in the plurality of cache lines in response to receiving a subsequent request to provide a second selected word that is aligned to a boundary of the second cache line by generating the clock signal and suppressing the load address signal.
An integrated circuit, comprising:
- a memory having memory cells organized by groups of words, wherein the groups of words are sequential, and wherein an initial group of the groups of words is selected by a first portion of an address and a word within the initial group is selected by a second portion of the address;
- and
- an address generator, coupled to the memory, for, in response to receiving a running clock and a load address signal, directing the memory to provide the words of the initial group in a wrap sequence beginning with the word selected by the second portion of the address, and providing one or more words of a second group of the groups of words in a linear sequence, wherein the second group follows in sequence from the initial group.
A memory characterized by bursting groups of words having a burst mode in which, in response to an address and a running clock, an initial burst of a group of words is in a wrap sequence and an immediately following burst is in a linear sequence.
A method of filling sequential first and second lines in a cache, wherein each of the first and second lines comprises a plurality of words, comprising:
- loading the plurality of words of a first of the first and second lines in a wrap sequence in response to providing a load address signal;
- and
- loading the plurality of words of a second of the first and second lines in a linear sequence by suppressing the load address signal.
A method of providing groups of words from a memory in response to an initial address that is misaligned with a boundary of an initial group of words, comprising:
- providing the initial group of words, after an access delay, in response to a running clock, the initial address, and a load address signal in a wrap sequence;
- and
- providing words of a first subsequent group that immediately follows the initial group in a linear sequence beginning at a boundary of the first subsequent group in response to the running clock without the access delay.
Dependencies are inferred from the claim text.