Multiprocessor interrupt handling system and method

A computer system having an interrupt handling apparatus, the computer system comprising:

• one or more processors;
• one or more hardware devices that are capable of interrupting the one or more processors using an interrupt signal;
• an interrupt controller that is capable of handling the interrupts from the one or more hardware devices and capable of independently generating a low priority interrupt signal and a high priority interrupt signal for each processor;
• the interrupt controller further comprising means for independently enabling the interrupt signal for each processor and means for independently assigning a priority to each interrupt signal destined for any processor wherein a particular interrupt signal is capable of being routed to either processor and is capable of being assigned a low priority or a high priority.

A method for interrupt handling in a multiple processor system, the method comprising:

• assigning the interrupt signal to one of the multiple processors based on availability of each processor;
• assigning a priority level to the interrupt signal wherein the priority is selected from one or more different priorities;
• and
• routing the interrupt signal with the assigned priority level to the assigned processor.

A computer system, comprising:

• a first processor;
• a second processor;
• a peripheral controller having a first bus that is capable of connecting the first processor to a set of peripheral resources and a second bus that is capable of connecting the second processor to the same set of peripheral resources wherein each peripheral in the set of peripheral resources is capable of generating an interrupt signal;
• the peripheral controller further comprising an interrupt controller that is capable of handling the interrupts from the set of peripheral resources and software interrupts and capable of independently generating a low priority interrupt signal and a high priority interrupt signal for each processor from the peripheral and software interrupts, the interrupt controller further comprising a first processor enable device that is capable of enabling the interrupt signals for the first processor, a second processor enable device that is capable of enabling the interrupt signals for the second processor, a first processor priority device that is capable of assigning a priority to the interrupt signals for the first processor and a second processor priority device that is capable of assigning a priority to the interrupt signals for the second processor wherein a particular interrupt signal is capable of being routed to either processor and is capable of being assigned a low priority or a high priority.

A computer system, comprising:

• a first processor;
• a second processor;
• a peripheral controller comprising first communications means that is capable of connecting the first processor to a set of peripheral resources and a second communications means that is capable of connecting the second processor to the same set of peripheral resources wherein each peripheral in the set of peripheral resources is capable of generating an interrupt signal;
• the peripheral controller further comprising an interrupt controller that is capable of handling the interrupts from the set of peripheral resources and software interrupts and capable of independently generating a low priority interrupt signal and a high priority interrupt signal for each processor from the peripheral and software interrupts, the interrupt controller further comprising means for enabling the interrupt signals for the first processor, means for enabling the interrupt signals for the second processor, means for assigning a priority to the interrupt signals for the first processor and means for assigning a priority to the interrupt signals for the second processor wherein a particular interrupt signal is capable of being routed to either processor and is capable of being assigned a low priority or a high priority.