Cross bar multipath resource controller system and method
AssigneeNVIDIA Corporation
InventorsJason Seung-Min Kim, Robert Alan Bignell
Life of this patent
Estimating the term…
Abstract
A cross bar multipath resource controller system and method permit multiple processors in a computer system to access various resource of the computer system, such as memory or peripherals, with zero blocking access. In particular, each processor has its own bus so that the processors can each independently access different resources in the computer system simultaneously.
Claims27
A computer system having a multipath cross bar bus, comprising:
- one or more processors;
- one or more resources capable of being shared by the one or more processors;
- and
- a resource controller and bus that is connected to each resource and to each processor wherein the resource controller is capable of permitting each processor to simultaneously access a different resource from the one or more resources.
An apparatus for controlling the access to one or more computing resources by one or more processor;
- the apparatus comprising a resource controller and bus that is connected to each resource and to each processor wherein the resource controller is capable of permitting each processor to simultaneously access a different resource from the one or more resources.
An apparatus for controlling the access to one or more memory resources by one or more processors, the controller comprising a memory resource controller and bus that is connected to each memory resource and to each processor so wherein the memory resource controller is capable of permitting each processor to simultaneously access a different resource from the one or more memory resources.
An apparatus for controlling access by one or more processors to one or more peripheral resources, the apparatus comprising a peripheral resource controller and bus that is connected to each peripheral resource and to each processor so wherein the resource controller is capable of permitting each processor to simultaneously access a different peripheral resource from the one or more peripheral resources.
A computer system, comprising:
- a first processor capable of executing a set of instructions;
- a second processor capable of executing a set of instructions;
- a multipath memory controller having a first bus that is capable of connecting the first processor to a set of memory resources and a second bus that is capable of connecting the second processor to the same set of memory resources wherein the first and second processors are capable of simultaneously accessing different memory resources;
- and
- a multipath peripheral controller having a first bus that is capable of connecting the first processor to a set of peripheral resources and a second bus that is capable of connecting the second processor to the same set of peripheral resources wherein the first and second processors are capable of simultaneously accessing different peripheral resources.
Dependencies are inferred from the claim text.