Modification to reconfigurable functional unit in a reconfigurable chip to perform linear feedback shift register function

An implementation of a linear feedback shift register on a reconfigurable chip wherein a first reconfigurable functional unit is adapted to provide at least one input bit to a second reconfigurable functional unit, the second reconfigurable functional unit having a modified input multiplexer unit that can select a combined value, the combined value including some of the bits from an output of the second reconfigurable functional unit and the at least one input bit from the first reconfigurable functional unit.

An implementation of a linear feedback shift register on a reconfigurable chip wherein a first reconfigurable functional unit is configured to add an input value to itself so that a carry bit contains the most significant bit of the input value, the second reconfigurable functional unit having a modified input multiplexer unit configured to select a combined value, the combined value including all but one bit of the output of the second reconfigurable functional unit and the carry bit from the first reconfigurable functional unit, wherein if the most significant bit of the output of the second reconfigurable functional unit is in a predetermined state, the second reconfigurable functional unit is configured to provide a mask value from a register and the second reconfigurable functional unit is configured to exclusive-OR the combined value to the mask value to produce an new output value.