Vertical gate transistors in pass transistor programmable logic arrays

A method for forming a programmable logic array, comprising:

• forming a first logic plane that receives a number of input signals, wherein forming the first logic plane includes forming a plurality of logic cells arranged in rows and columns that a re interconnected to provide a number of logical outputs;
• forming a second logic plane having a plurality of logic cells arranged in rows and columns that receive a number of output signals from the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function;
• and
• wherein forming the logic cells includes:
• forming a source region, a drain region, and a depletion mode channel region therebetween in a horizontal substrate;
• forming a first vertical gate located above a first portion of the depletion mode channel region and separated from the depletion mode channel region by a first oxide thickness;
• forming a second vertical gate located above a second portion of the depletion mode channel region and separated from the depletion mode channel region by a second oxide thickness, and
• forming a third vertical gate located above a third portion of the depletion mode channel region and separated from the depletion mode channel region by the second oxide thickness.

A method for operating a programmable logic array, comprising:

• applying a number of input signals to a number of logic cells in a first logic plane, wherein each logic cell includes a source region, a drain region, a depletion mode channel region therebetween, and a number of vertical gates located above different portions of the depletion mode channel region, wherein at least one of the vertical gates is separated from the depletion mode channel by a first oxide thickness, wherein at least one of the vertical gates is separated from the depletion mode channel by a second oxide thickness, and wherein applying a number of input signals to the number of logic cells in the first logic plane includes applying a potential to the number of vertical gates in each logic cell;
• outputting a number of output signals from the first logic plane to a number of logic cells in a second logic plane, wherein each logic cell in the second logic plane includes a source region, a drain region, a depletion mode channel region therebetween, and a number of vertical gates located above different portions of the depletion mode channel region, wherein at least one of the vertical gates is separated from the depletion mode channel by a first oxide thickness, wherein at least one of the vertical gates is separated from the depletion mode channel by a second oxide thickness, and wherein outputting a number of output signals from the first logic plane to a number of logic cells in a second logic plane includes applying a potential to the number of vertical gates for the logic cells in the second logic plane;
• and
• wherein the number of logic cells in the second logic plane are arranged in rows and columns to receive the output signals from the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function.

A method for operating a programmable logic array, comprising:

• applying a number of input signals to a number of logic cells in a first logic plane, wherein applying a number of input signals to the number of logic cells in the first logic plane includes applying a potential to a number of vertical gates located above different portions of a horizontal depletion mode channel, wherein at least one of the vertical gates is separated from the depletion mode channel by a first oxide thickness, and wherein at least one of the vertical gates is separated from the depletion mode channel by a second oxide thickness;
• outputting a number of output signals from the first logic plane to a number of logic cells in a second logic plane, wherein outputting the number of output signals from the first logic plane to the number of logic cells in the second logic plane includes applying a potential to a number of vertical gates located above different portions of a horizontal depletion mode channel, wherein at least one of the vertical gates is separated from the depletion mode channel by a first oxide thickness, and wherein at least one of the vertical gates is separated from the depletion mode channel by a second oxide thickness;
• wherein the number of logic cells in the second logic plane are arranged in rows and columns to receive the output signals of the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function;
• using at least one of the number of vertical gates in any logic cell as a passing line such that a potential on the passing line does not effect conduction in the depletion mode channel;
• and
• using at least two of the number of vertical gates in any logic cell as a number of active inputs such that the active inputs control conduction in the depletion mode channel.