Stacked LDD high frequency LDMOSFET
AssigneeInstitute of Microelectronics
InventorsJun Cai, Pang Dow Foo, Narayanan Balasubramanian
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Abstract
A novel silicon RF LDMOSFET structure based on the use of a stacked LDD, is disclosed. The LDD has been modified from a single layer of N type material to a stack of three layers. These are upper and lower N type layers with a P type layer between them. The upper N type layer is heavily doped to reduce the on-resistance of the device, while the lower N type layer is lightly doped to reduce the output capacitance, thereby improving the high frequency performance. The middle P layer is heavily doped which allows it to bring about pinch-off of the two N layers, thereby raising the device's breakdown voltage. A process for manufacturing the device, as well as experimental data concerning its performance are also given.
Claims23
A multi-layer lateral double diffused structure, comprising:
- a topmost layer of N type silicon;
- a middle layer of P type silicon;
- and
- a bottommost layer of N type silicon,
- said structure being part of a power MOSFET that has a gate and a drain;
- and
- said structure being located between said gate and said drain.
A stacked high frequency LDMOSFET, comprising:
- a P+ silicon substrate on which has been deposited an epitaxial layer of P− silicon having an upper surface;
- a P+ sinker region that extends downwards from said upper surface through the P− epitaxial layer into the P+ substrate;
- a polysilicon gate pedestal over said upper surface, there being a layer of gate oxide between the pedestal and the upper surface;
- an N+ source region on a first side of said gate pedestal and a P− body under the gate extending into said source region;
- a drain region on an opposing second side of the gate there being a separation region between the gate and the drain region;
- in said separation region, a first N type LDD layer that extends downward from said upper surface to a first interface;
- in said separation region, a P type LDD layer that extends downward from said first interface to a second interface;
- and
- in said separation region, a second N type LDD layer that extends downward from said second interface to a third interface.
A process for manufacturing an LDMOSFET, comprising:
- providing a P+ silicon substrate and depositing thereon an epitaxial layer of P− silicon having an upper surface;
- forming a P+ sinker region that extends downwards from said upper surface through the P− epitaxial layer into the P+ substrate, by means of ion implantation through a mask, followed by a drive-in diffusion;
- growing a layer of gate oxide on said upper surface and then depositing thereon a layer of phosphorus doped polysilicon;
- patterning and etching said polysilicon layer to form a gate pedestal and then removing all gate oxide not under said gate pedestal;
- by means of double diffusion through a mask, forming an N+ source region on a first side of said gate pedestal and a P− body under the gate and extending into said source region;
- by ion implantation through a mask, forming a drain region on an opposing second side of the gate there being a separation region between the gate and the drain region;
- in said separation region, forming, by ion implantation, a first N type LDD layer that extends downward from said upper surface to a first interface;
- in said separation region, forming, by ion implantation, a P type LDD layer that extends downward from said first interface to a second interface;
- and
- in said separation region, forming, by ion implantation, a second N type LDD layer that extends downward from said second interface to a third interface.
Dependencies are inferred from the claim text.