Method of fabricating an electrostatic vertical and torsional actuator using one single-crystalline silicon wafer

A method of fabricating an electrostatic vertical and torsional actuator using the MEMS fabrication technology, comprising the following steps:

• step (a) of depositing silicon etch mask 1 on a silicon wafer and patterning it by the first photolithography process, thereby determining all the planar dimensions of the vertical or torsional actuator from the same photomask;
• step (b) of depositing silicon etch mask 2 on top of the already patterned etch mask 1 of step (a), and patterning it by the second photolithography process, making the upper comb electrodes of the vertical or torsional actuator to be completely covered by the silicon etch mask 2, while parts of silicon substrate is exposed;
• step (c) of performing the first silicon etching by an amount of t1, during which the silicon etch mask 2 and the parts of the silicon etch mask 1 that is not covered with the silicon etch mask 2 are also simultaneously etched, such that the silicon etch mask 1 has different thicknesses between the parts that are covered with the silicon etch mask 2 and the parts that are not covered with the silicon etch mask 2;
• step (d) of removing the silicon etch mask 2;
• step (e) of determining the thickness of the upper electrode by performing the second silicon etching by an amount of t2 in the state where the silicon etch mask 2 has been removed at the step (d);
• step (f) of depositing a wall protection layer on the vertical sidewalls of the structure which has been formed at the step (e);
• step (g) of determining the vertical gap between the substrate and the lower electrode by performing the third silicon etching by an amount of t3 after the step (f);
• step (h) of laterally underetching silicon parts that are not covered with the protection layer and that are exposed in the step (g), in the horizontal direction using aqueous alkaline etchant, such that the body of the structure and various combs are released from the main wafer substrate;
• step (i) of, to the structure formed through the step (h), etching the silicon etch mask 1 by the amount of the thickness of the silicon etch mask 1 at the thinner parts within the silicon etch mask 1, where the thickness difference of the silicon etch mask 1 is caused by the etching of the exposed part of the silicon etch mask 1 which are not covered with the silicon etch mask 2, at the step (c) and determining the vertical offset between the upper electrode and the lower electrode by performing the fourth silicon etching by an amount of t4;
• and
• step (j) of removing the wall protection layer, which has been formed at the step (f), and removing the silicon etch mask 1, which is formed at the step (a).