Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching
AssigneeInternational Business Machines Corporation
InventorsJeffrey J. Brown, Sadanand Vinayak Deshpande, David V. Horak, Maheswaran Surendra, Len Y. Tsou, Qingyun Yang, Chienfan Yu, Ying Zhang
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Abstract
A method of fabricating an electronic chip on a wafer in which a first mask at a predetermined lower resolution is developed on the wafer and then etched under a first set of conditions for a predetermined period to achieve a mask that is below the resolution limit of current lithography. The etched mask is then used as a hard mask for etching material on a lower layer.
Claims16
A method of fabricating an electronic chip on a wafer, comprising:
- developing on a surface of said wafer a first mask at a predetermined lower resolution;
- and
- etching said first mask under a first set of conditions for a predetermined period to achieve a higher resolution mask.
A method of fabricating at least one electronic device or circuit on a wafer, comprising:
- developing a first mask on an outer surface of said wafer or of a layer of material deposited on said surface to define a pattern for at least part of a structure or circuit component for said electronic device or circuit, said first mask comprising an organic photo-sensitive resist material;
- performing a trimming process on said first mask to adjust dimensions of said pattern;
- and
- using said trimmed first mask as a hard mask for an etching process to remove material from at least one layer below said hard mask.
A method of controlling line width variation tolerances during fabrication of electronic devices or circuits on a wafer, comprising:
- developing a first mask on an outer surface of said wafer or of a layer of material deposited on said surface to define a pattern for at least part of a structure or circuit component for said electronic device or circuit, said first mask comprising an organic photo-sensitive resist material;
- performing a trimming process on said first mask to adjust dimensions of features of said first mask;
- and
- using said trimmed first mask as a hard mask for an etching process to remove material from at least one layer below said hard mask.
A method, during fabrication of electronic devices or circuits on a wafer, said devices or circuits having both isolated features and nested features, of controlling line width variation tolerances of said isolated features relative to said nested features while independently achieving a target critical dimension, comprising:
- establishing a first set of conditions for an RF etch process that achieves said target critical dimension;
- and
- controlling a level of said RF power as a parameter to independently control said line width variation tolerance of said isolated features relative to said nested features.
Dependencies are inferred from the claim text.