Cryptographic accelerator
AssigneeAEP Systems Limited
InventorsChristopher Fairclough, Francis Flanagan
Life of this patent
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Abstract
A cryptographic accelerator (1) has a host interface (2) for interfacing with a host sending cryptographic requests and receiving results. A CPU (3) manages the internal logical unit in an exponentiation sub-system (7) having modulator exponentiators (30). The exponentiators (30) are chained together up to a maximum of four, in a block (20). There are ten blocks (20). A scheduler uses control registers and an input buffer to perform the scheduling control.
Claims23
A cryptographic accelerator comprising a host interface (2) comprising means for interfacing with a host system having applications requesting cryptographic operations, means for performing exponentiation, and means in the host interface for routing request responses to the host system, characterised in that,
- the accelerator comprises a plurality of logical units (6-9), including an exponentiation sub-system (7), and
- the accelerator further comprises a CPU (5) connected between the host interface (2) and the logical units (6-9) and comprising means for managing operation of the logical units.
Dependencies are inferred from the claim text.