Method and system for regulating the decision threshold and the sampling clock phase of a data regenerator for a binary signal
AssigneeSiemens Aktiengesellschaft
InventorsHarald Bock, Wolfgang Peisl, Andreas Faerbert
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Abstract
A method and system for regulating the decision threshold and the sampling clock phase of a data regenerator for a binary signal, wherein error correction signals for erroneous 1-bits and 0-bits are used for regulating the decision threshold of a decision stage, and further phase correction signals between transitions of binary signals serve for the phase regulation of a sampling clock signal.
Claims14
A method for regulating a decision threshold in a sampling of a binary signal by evaluation of error correction signals, the method comprising the steps of:
- counting both a number of 1-bits detected as erroneous and a number of 0-bits detected as erroneous;
- evaluating the number of 1-bits detected as erroneous and the number of 0-bits detected as erroneous;
- and
- adjusting the decision threshold correspondingly to achieve an optimum ratio of the number of 1-bits detected as erroneous and the number of 0-bits detected as erroneous.
A method for regulating a relative phase of a sampling clock signal with respect to a phase of a binary signal by evaluation of error correction signals, the method comprising the steps of:
- counting and evaluating a number of bits detected as erroneous before a transition between binary states and a number of bits detected as erroneous after a transition between the binary states;
- and
- adjusting the phase of the sampling clock signal such that at least approximately the same number of bits detected as erroneous occurs before and after the transition between the binary states.
A system for regulating a decision threshold of a data regenerator having a decision stage, to which a binary signal and a comparison signal are fed, the system comprising:
- a sampling flip-flop having a data input connected to an output of the decision stage;
- a controllable clock regenerator which generates a sampling clock signal for the sampling flip-flop;
- an error correction device for controlling the controllable clock regenerator;
- and
- a regulator, a first correction signal being fed to the regulator from the error correction device which indicates a correction of a 1-bit, and a second correction signal being fed to the regulator from the error correction device which indicates a correction of a 0-bit, wherein the regulator separately sums and assesses the first and second correction signals and generates a control signal which determines a magnitude of the comparison signal.
A system for regulating a phase of a sampling clock signal, the system comprising:
- a clock regenerator for generating the sampling clock signal;
- an error correction device for controlling the clock regenerator;
- a sampling flip-flop into which a binary signal is latched via the sampling clock signal;
- and
- a regulator, a first phase correction signal being fed to the regulator from the error correction device which indicates a correction of a bit before a signal transition between two binary states, and a second phase correction signal being fed to the regulator which indicates a correction of a bit after a signal transition between two binary states, the regulator counting the correction signals and comparing the sums to generate a phase correction signal which generates the phase of the sampling clock signal such that at least approximately a same number of correction signals occurs before and after a transition between the binary state.
Dependencies are inferred from the claim text.