Low-cost high-speed multiplier/accumulator unit for decision feedback equalizers

Method for performing multiplication in a decision feedback equalizer device implementing a filter unit for performing convolution operations between filter coefficients and one of a plurality of original discrete digital level values, said method comprising:

• a) decoding a discrete digital level value to be multiplied by a filter coefficient, and implementing logic for generating control signals according to said digital level value;
• b) performing two parallel operations, each operation including multiplying said filter coefficient by either +1/−1 in accordance with said control signals for generating two intermediate results, and, corresponding operations for multiplying a corresponding intermediate result by +1 or zero (0) in accordance with a control signals and generating respective first and second intermediate output results in parallel;
• c) shifting bits to effect a multiplication of one of said first and second intermediate output result with a discrete digital value different than any of said original plurality of discrete digital level values, and generating a third intermediate result;
• and,
• d) adding the results of said third and the other of said first or second intermediate results to obtain a final multiplication result, whereby said final multiplication result of said filter coefficient with said original discrete digital level value is achieved at a greater speed with less redundancy.

A multiplier device for multiplying one of a set of discrete digital level values with a filter coefficient comprising:

• decoder device for receiving a discrete digital level value to be multiplied and generating control signals according to said digital level value;
• inverter circuit providing two parallel operations, each operation including multiplying said determined number by either +1/−1 in accordance with said control signals for generating two intermediate results;
• multiplier circuit receiving said two intermediate results and providing respective parallel operations for multiplying a corresponding intermediate result of said inverter circuit by +1 or zero (0) in accordance with a control signals and generating respective further intermediate results;
• logic circuit for shifting bits of one further intermediate result to effect a multiplication of one said further intermediate output result with a discrete digital level value different than any of said original plurality of discrete digital level values;
• and,
• an accumulator device for adding the results of said logic circuit shift multiplication with the other said further intermediate output result to obtain a final multiplication result.