Synchronous semiconductor memory device for controlling cell operations by using frequency information of a clock signal
AssigneeHynix Semiconductor Inc.
InventorJeong Su Jeong
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Abstract
The synchronous semiconductor memory device includes a frequency information generating circuit for outputting a plurality of frequency information corresponding to the frequency of the clock signal in response to a state control signal and an internal address in order to adjust a point of time to disable and precharge a word line by a frequency information corresponding to a frequency of a clock signal. Therefore, even though a high frequency clock signal is inputted, the word line is disabled and precharged when a cell node is charged enough. In this way, it can prevent from failing cell operations and promotes operation efficiency of the synchronous semiconductor memory device.
Claims10
A synchronous semiconductor memory device comprising:
- a state control circuit producing output signals for setting operation states;
- an address buffer for buffering an inputted address;
- a mode register producing output signals for setting operation modes in response to an output signal from said state control circuit and an inputted address from said address buffer;
- a frequency information generating circuit for detecting and outputting frequency information of a clock signal in response to the output signal of said state control circuit and the inputted address of said address buffer;
- and
- a driving circuit for activating a word line in accordance with the output signal of the state control circuit, an output signal of the mode register, and the frequency information of the frequency information generating circuit.
Dependencies are inferred from the claim text.