Dynamic random access memory with low power consumption

A low power consumption type dynamic random access memory operated by an external power supply voltage, the dynamic access memory comprising:

• an internal voltage circuit including an internal voltage generator for converting the external power supply voltage applied thereto into an internal power supply voltage, said internal voltage circuit being deactivated in response to a first control signal received thereto;
• an input circuit having an input terminal receiving an input signal and a input transistor having a gate connected to the input terminal;
• a memory array for storing data, said memory cell being operated by the internal power supply voltage;
• a peripheral circuit coupled to said memory array and said input circuit for controlling said memory array, said peripheral circuit being operated by the internal power supply voltage;
• and
• an output circuit coupled to said peripheral circuit for outputting an output signal, said output circuit being operated by the external power supply voltage, said output circuit including an output terminal and an output transistor having a source connected to be applied to the external power supply voltage, a drain connected to the output terminal and a gate, wherein said output transistor has a parasitic diode formed so as to be forward biased from the drain to the source of the output transistor, and wherein said output transistor is controlled to be in a high impedance condition in response to a second control signal received at the gate thereof.

A low power consumption type dynamic random access memory operated by an external power supply voltage, the dynamic access memory comprising:

• a first internal voltage circuit including a first internal voltage generator for converting the external power supply voltage applied thereto into an internal power supply voltage, said first internal voltage circuit being deactivated in response to a first control signal received thereto;
• a second internal voltage circuit including a second internal voltage generator for converting the internal power supply voltage applied thereto into an internal voltage, said second internal voltage circuit being deactivated in response to the first control signal received thereto;
• an input circuit for receiving an input signal;
• a memory array for storing data, said memory cell being operated by the internal power supply voltage and the internal voltage;
• a peripheral circuit coupled to said memory array and said input circuit for controlling said memory array, said peripheral circuit being operated by the internal power supply voltage and the internal voltage;
• and
• an output circuit coupled to said peripheral circuit for outputting an output signal, said output circuit being operated by the external power supply voltage, said output circuit being controlled to be in a high impedance condition in response to a second control signal received thereto.