Semiconductor device with reduced current consumption in standby state
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTsukasa Ooishi, Takaharu Tsuji, Masatoshi Ishikawa, Hideto Hidaka, Hiroshi Kato
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Abstract
A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.
Claims17
A semiconductor device transmitting/receiving data in a normal mode and refreshing stored data with reduced current consumption in a power down mode, comprising:
- a memory array including a plurality of memory cells arranged in a matrix of rows and columns;
- a first peripheral circuit inputting/outputting storage data in said memory cells in said normal mode and stopping operation in said power down mode for reducing current consumption;
- and
- a second peripheral circuit controlling refresh of data stored in said memory cells in said power down mode.
Dependencies are inferred from the claim text.