Voltage-level shifter and semiconductor memory using the same

A voltage-level shifter comprising:

• a first power supply terminal to which a first potential is supplied;
• a second power supply terminal to which a second potential is supplied, the second potential being lower than the first potential;
• a first input terminal to which a first input signal is supplied, the first input signal having a high and a low level according to the first and the second potentials;
• a second input terminal to which a second input signal is supplied, the second input signal being an inverted signal of the first input signal;
• a first PMOS transistor having a source connected to the first power supply terminal, a gate connected to the first input terminal, and a drain connected to a first output terminal for outputting a first output signal;
• a second PMOS transistor having a source connected to the first power supply terminal, a gate connected to the second input terminal, and a drain connected to a second output terminal for outputting a second output signal that is an inverted signal of the first output signal;
• a first NMOS transistor having a drain connected to the first output terminal and a gate connected to the second output terminal;
• a second NMOS transistor having a drain connected to the second output terminal and a gate connected to the first output terminal;
• a third NMOS transistor having a source connected to the second power supply terminal, a drain connected to the source of the first NMOS transistor, and a gate connected to the first input terminal;
• and
• a fourth NMOS transistor having a source connected to the second power supply terminal, a drain connected to the source of the second NMOS transistor, and a gate connected to the second input terminal.

A voltage-level shifter comprising:

• a first power supply terminal to which a first potential is supplied;
• a second power supply terminal to which a second potential is supplied, the second potential being lower than the first potential;
• a first input terminal to which a first input signal is supplied, the first input signal having a high and a low level according to the first and the second potentials;
• a second input terminal to which a second input signal is supplied, the second input signal being an inverted signal of the first input signal;
• a first NMOS transistor having a source connected to the second power supply terminal, a gate connected to the first input terminal, and a drain connected to a first output terminal for outputting a first output signal;
• a second NMOS transistor having a source connected to the second power supply terminal, a gate connected to the second input terminal, and a drain connected to a second output terminal for outputting a second output signal that is an inverted signal of the first output signal;
• a first PMOS transistor having a drain connected to the first output terminal and a gate connected to the first input terminal;
• a second PMOS transistor having a drain connected to the second output terminal and a gate connected to the second input terminal;
• a third PMOS transistor having a source connected to the first power supply terminal, a drain connected to the source of the first PMOS transistor, and a gate connected to the second output terminal;
• and
• a fourth PMOS transistor having a source connected to the first power supply terminal. a drain connected to the source of the second PMOS transistor, and a gate connected to the first output terminal.

A voltage-level shifter comprising:

• a first power supply terminal to which a first potential is supplied;
• a second power supply terminal to which a second potential is supplied, the second potential being lower than the first potential;
• a first input terminal to which a first input signal is supplied, the first input signal having a high and a low level according to the first and the second potentials;
• a second input terminal to which a second input signal is supplied, the second input signal being an inverted signal of the first input signal;
• a first NMOS transistor having a source connected to the first power supply terminal, a gate connected to the first input terminal, and a drain connected to a first output terminal for outputting a first output signal;
• a second NMOS transistor having a source connected to the second power supply terminal, a gate connected to the second input terminal, and a drain connected to a second output terminal for outputting a second output signal that is an inverted signal of the first output signal;
• a first PMOS transistor having a drain connected to the first output terminal and a gate connected to the second output terminal;
• a second PMOS transistor having a drain connected to the second output terminal and a gate connected to the first output terminal;
• a third PMOS transistor having a source connected to the first power supply terminal. a drain connected to the source of the first PMOS transistor, and a gate connected to the first input terminal;
• and
• a fourth PMOS transistor having a source connected to the first power supply terminal, a drain connected to the source of the second PMOS transistor, and a gate connected to the second input terminal.

A semiconductor memory comprising:

• a memory cell array having a plurality of electrically-rewritable memory cells.
• a decoder that decodes an address signal to output a decoded output signal for selecting at least one of word lines and bit lines of the memory cell array;
• a first voltage-level shifter that shifts a high level of the decoded output signal for selecting at least one of the word lines to a further high level according to an operation mode to output a first voltage-level shifted output signal:
• a second voltage-level shifter that shifts a low level of the first voltage-level shifted output signal to a further low level according to the operation mode to output a second voltage-level shifted output signal;
• and
• a word line driver that is controlled by the second voltage-level shifted output signal to drive the selected word line,
• wherein the first voltage-level shifter includes:
• a first power supply terminal to which a first potential is supplied;
• a second power supply terminal to which a second potential is supplied, the second potential being lower than the first potential;
• a first input terminal to which the decoded output signal is supplied, the decoded output signal having a high and a low level according to the first and the second potentials;
• a second input terminal, to which a second input signal is supplied, the second input signal being an inverted signal of the decoded output signal;
• a first NMOS transistor having a source connected to the second power supply terminal, a gate connected to the first input terminal, and a drain connected to a first output terminal for outputting a first output signal as the first voltage-level sifted output signal;
• a second NMOS transistor having a source connected to the second power supply terminal, a gate connected to the second input terminal, and a drain connected to a second output terminal for outputting a second output signal that is an inverted signal of the first output signal;
• a first PMOS transistor having a drain connected to the first output terminal and a gate connected to the first input terminal;
• a second PMOS transistor having a drain connected to the second output terminal and a gate connected to the second input terminal;
• a third PMOS transistor having a source connected to the first power supply terminal, a drain connected to the source of the first PMOS transistor, and a gate connected to the second output terminal;
• and
• a fourth PMOS transistor having a source connected to the first power supply terminal, a drain connected to the source of the second PMOS transistor. and a gate connected to the first output terminal.

A semiconductor memory comprising:

• a memory cell array having a plurality of electrically-rewritable memory cells:
• a decoder that decodes an address signal to output a decoded output signal for selecting at least one of word lines and bit lines of the memory cell array;
• a first voltage-level shifter that shifts a high level of the decoded output signal for selecting at least one of the word lines to a further high level according to an operation mode to output a first voltage-level shifted output signal;
• a second voltage-level shifter that shifts a low level of the first voltage-level shifted output signal to a further low level according to the operation mode to output a second voltage-level shifted output signal;
• and
• a word line driver that is controlled by the second voltage-level shifted output signal to drive the selected word line,
• wherein the second voltage-level shifter includes:
• a first power supply terminal to which a first potential is supplied;
• a second power supply terminal to which a second potential is supplied. the second potential being lower than the first potential;
• a first input terminal to which the first voltage-level shifted output signal is supplied, the first voltage-level shifted output signal having a high and a low level according to the first and the second potentials;
• a second input terminal to which a second input signal is supplied, the second input signal being an inverted signal of the first voltage-level shifted output signal;
• a first PMOS transistor having a source connected to the first power supply terminal, a gate connected to the first input terminal, and a drain connected to a first output terminal for outputting a first output signal as the second voltage-level shifted output signal;
• a second PMOS transistor having a source connected to the first power supply terminal, a gate connected to the second input terminal, and a drain connected to a second output terminal for outputting a second output signal that is an inverted signal of the first output signal;
• a first NMOS transistor having a drain connected to the first output terminal and a gate connected to the first input terminal;
• a second NMOS transistor having a drain connected to the second output terminal and a gate connected to the second input terminal;
• a third NMOS transistor having a source connected to the second power supply terminal, a drain connected to the source of the first NMOS transistor, and a gate connected to the second output terminal;
• and
• a fourth NMOS transistor having a source connected to the second power supply terminal. a drain connected to the source of the second NMOS transistor, and a gate connected to the first output terminal.

A semiconductor memory comprising:

• a memory cell array having a plurality of electrically-rewritable memory cells;
• a decoder that decodes an address signal to output a decoded output signal for selecting at least one of word lines and bit lines of the memory cell array;
• a first voltage-level shifter that shifts a low level of the decoded output signal for selecting at least one of the word lines to a further low level according to an operation mode to output a first voltage-level shifted output signal:
• a second voltage-level shifter that shifts a high level of the first voltage-level shifted output signal to a further high level according to the operation mode to output a second voltage-level shifted output signal;
• and
• a word line driver that is controlled by the second voltage-level shifted output signal to drive the selected word line,
• wherein the second voltage-level shifter includes:
• a first power supply terminal to which a first potential is supplied;
• a second power supply terminal to which a second potential is supplied, the second potential being lower than the first potential;
• a first input terminal to which the first voltage-level shifted output signal is supplied, the first voltage-level shifted output signal having a high and a low level according to the first and the second potentials;
• a second input terminal to which a second input signal is supplied, the second input signal being an inverted signal of the first voltage-level shifted output signal;
• a first NMOS transistor having a source connected to the second power supply terminal, a gate connected to the first input terminal, and a drain connected to a first output terminal for outputting a first output signal as the second voltage-level sifted output signal;
• a second NMOS transistor having a source connected to the second power supply terminal, a gate connected to the second input terminal, and a drain connected to a second output terminal for outputting a second output signal that is an inverted signal of the first output signal;
• a first PMOS transistor having a drain connected to the first output terminal and a gate connected to the first input terminal;
• a second PMOS transistor having a drain connected to the second output terminal and a gate connected to the second input terminal;
• a third PMOS transistor having a source connected to the first power supply terminal, a drain connected to the source of the first PMOS transistor, and a gate connected To the second output terminal;
• and
• a fourth PMOS transistor having a source connected to the first power supply terminal, a drain connected to the source of the second PMOS transistor, and a gate connected to the first output terminal.

A semiconductor memory comprising;

• a memory cell array having a plurality of electrically-rewritable memory cells:
• a decoder that decodes an address signal to output a decoded output signal for selecting at least one of word lines and bit lines of the memory cell array;
• a first voltage-level shifter that shifts a low level of the decoded output signal for selecting at least one of the word lines to a further low level according to an operation mode to output a first voltage-level shifted output signal;
• a second voltage-level shifter that shifts a high level of the first voltage-level shifted output signal to a further high level according to the operation mode to output a second voltage-level shifted output signal;
• and
• a word line driver that is controlled by the second voltage-level shifted output signal to drive the selected word line,
• wherein the first voltage-level shifter includes:
• a first power supply terminal to which a first potential is supplied:
• a second power supply terminal to which a second potential is supplied, the second potential being lower than the first potential;
• a first input terminal to which the decoded output signal is supplied, the decoded output signal having a high and a low level according to the first and the second potentials;
• a second input terminal to which a second input signal is supplied, the second input signal being an inverted signal of the first voltage-level shifted output signal;
• a first PMOS transistor having a source connected to the first power supply terminal, a gate connected to the first input terminal, and a drain connected to a first output terminal for outputting a first output signal as the first voltage-level shifted output signal;
• a second PMOS transistor having a source connected to the first power supply terminal, a gate connected to the second input terminal, and a drain connected to a second output terminal for outputting a second output signal that is an inverted signal of the first output signal;
• a first NMOS transistor having a drain connected to the first output terminal and a gate connected to the first input terminal;
• a second NMOS transistor having a drain connected to the second output terminal and a gate connected to the second input terminal;
• a third NMOS transistor having a source connected to the second power supply terminal, a drain connected to the source of the first NMOS transistor. and a gate connected to the second output terminal:
• and
• a fourth NMOS transistor having a source connected to the second power supply terminal, a drain connected to the source of the second NMOS transistor, and a gate connected to the first output terminal.