Integrated systems using vertically-stacked three-dimensional memory cells

Abstract

The preferred embodiments described herein relate to a monolithic integrated circuit comprising a three-dimensional memory array having a plurality of layers of memory cells stacked vertically above one another and above the substrate of the integrated circuit. Support circuitry for the three-dimensional memory array is formed in the substrate at least partially under the three-dimensional memory array and defines open area in the substrate under the three-dimensional memory array. In one preferred embodiment, one or more memory arrays are formed at least partially in the open area under the three-dimensional memory array, while in another preferred embodiment, logic circuitry implementing one or more functions is formed at least partially in the open area under the three-dimensional memory array. In yet another preferred embodiment, both one or more memory arrays and logic circuitry are formed at least partially in the open area under the three-dimensional memory array. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Dependencies are inferred from the claim text.