String programmable nonvolatile memory with NOR architecture

A method comprising, in a nonvolatile memory having NOR architecture and comprising a memory array including a plurality of memory cells arranged in rows and columns in NOR configuration, the memory cells arranged in a same column being connected to one of a plurality of bit lines;

• and a column decoder including a plurality of selection stages, each of which is connected to respective bit lines, the method comprising:
• generating a programming voltage;
• generating first bit line addressing signals,
• selecting only one bit line for each selection stage according to said first bit line addressing signals and
• supplying said programming voltage to said only one bit line;
• generating second bit line addressing signals;
• and
• selecting a plurality of bit lines for each selection stage according to said bit line addressing signals;
• and
• simultaneously supplying a programming voltage to said plurality of bit lines.

A method for programming a plurality of memory cells, the plurality of memory cells comprising a string of memory cells, wherein the memory cells are in a NOR type configuration, comprising:

• storing a first word of data having a number of bits, in a first plurality of registers, wherein the first plurality of registers equals the number of bits in the first word, and each register stores one of the number of bits of the first word;
• storing a second word of data having the number of bits, in a second plurality of registers, wherein the second plurality of registers equals the number of bits in the first word, and each of the second plurality of registers stores one of the number of bits of the second word;
• providing a means wherein each one of the first plurality of registers and each one of the second plurality of registers is associated with a corresponding one of the plurality of memory cells;
• and
• simultaneously writing each one of the number of bits stored in the first plurality of registers and each one of the number of bits stored in the second plurality of registers into the memory cells associated with the respective ones of the first and second plurality of registers.

A device comprising:

• a plurality of memory cells arranged in a row and columns, in NOR configuration, each one of the plurality of memory cells configured to accept a data bit at a programming input in the presence of an enable voltage at a program enable input, and configured to store the bit of data as one of a plurality of logic levels;
• a plurality of bit registers, each configured to receive, in the presence of a read enable signal at a first enable input, a single bit of data at a data input and hold the bit of data, as one of a plurality of logic levels, and further configured, in the presence of a write enable signal at a second enable input, to present the bit of data at an output;
• connection means for connecting the output of each one of the plurality of bit registers to the programming input of a corresponding one of the plurality of memory cells;
• a data source for supplying a stream of data bits to the inputs of the bit registers;
• timing means for supplying the read enable signal, sequentially, to enable each one of the plurality of bit registers to receive a successive one of the stream of data bits;
• and
• enabling means for providing the write enable signal at the second enable input of each of the plurality of bit registers simultaneously, and further, for concurrently providing the enable voltage at the program enable input of each of the plurality of memory cells.