Word programmable EEPROM memory comprising column selection latches with two functions
AssigneeSTMicroelectronics S.r.l.
InventorsBertrand Bertrand, Mohamad Chehadi, David Naura
Life of this patent
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Abstract
An electrically programmable and erasable memory includes memory cells connected to word lines and to bit lines arranged in columns. Bit lines selection transistors are driven by bit lines selection signals. Column selection latches each includes a locking element for a column selection signal and a circuit for delivering a gate control signal which depends on the output of the locking element. Each column selection latch delivers, in addition to a gate control signal, a bit lines selection signal. This signal depends on the output of the locking element at least during programming and reading phases of the memory cells.
Claims17
Electrically programmable and erasable memory comprising:
- memory cells (CEi,j) connected to word lines (WLi) and bit lines (BLj) arranged in columns (COLk),
- bit lines selection transistors (TSBLj) driven by bit lines selection signals (BLSk), and
- column selection latches (LSCIk) each receiving a column selection signal (SELk) delivered by a column decoder (CDEC) and delivering a gate control signal (CGSk) applied to the memory cells of a column, and comprising each a locking element (MEk) of the column selection signal (SELk) and means (T12) for conferring to the gate control signal (CGSk) a value which depends on the output of the locking element,
- characterised in that each column selection latch (LSCIk) comprises means (INV3, T14) for delivering, in addition to the gate control signal (CGSk), a bit lines selection signal (BLSk) whose value depends on the output of the locking element (MEk) at least during programming and reading phases of memory cells.
Method of selecting bit lines (BLj) in an electrically programmable and erasable memory comprising:
- memory cells (CEi,j) connected to word lines (WLi) and bit lines (BLj) arranged in columns (COLk),
- bit lines selection transistors (TSBLj) driven by bit lines selection signals (BLSk), and
- column selection latches (LSCIk) each receiving a column selection signal (SELk) delivered by a column decoder (CDEC) and delivering a gate control signal (CGSk) applied to the memory cells of a column, and comprising each a locking element (MEk) of the column selection signal (SELk) and means (T12) for conferring to the gate control signal (CGSk) a value which depends on the output of the locking element,
- characterised in that, in each column selection latch (LSCIk), means (INV3, T14) are provided for delivering, in addition to the gate control signal (CGSk), a bit lines selection signal (BLSk) whose value depends on the output of the locking element (MEk) at least during programming and reading phases of memory cells.
Dependencies are inferred from the claim text.