Current switching sensor detector

A circuit for detecting a logical state of a switching circuit, comprising:

• a current sensing amplifier for detecting a current flow state between a first and second terminals, said current sensing amplifier also indicating said current flow state on a data terminal;
• a first current limiter having a third and fourth terminals and a first control terminal for accepting a first control signal to controllably limiting current flow between said third and fourth terminals, said first current limiter being coupled in series with the current sensing amplifier between said second and third terminals;
• a voltage regulator having a fifth and sixth terminals, said voltage regulator being coupled in series with said first current limiter between said fourth and fifth terminals and said sixth terminal being adapted to be coupled to the switching circuit;
• a current limit control circuit coupled to said first control terminal and for supplying said first control signal.

A memory system, comprising:

• a plurality of content addressable memory (CAM) cells arranged into an array, each of said CAM cells further comprising a storage element and a match detection circuit for detecting a match between incoming data and data stored in said storage element, said match detection circuit further comprising,
• a logic switch;
• a current sensing amplifier for detecting a current flow state between a first and second terminals, said current sensing amplifier also indicating said current flow state on a data terminal;
• a first current limiter having a third and fourth terminals and a first control terminal for accepting a first control signal to controllably limiting current flow between said third and fourth terminals, said first current limiter being coupled in series with the current sensing amplifier between said second and third terminals;
• a voltage regulator having a fifth and sixth terminals, said voltage regulator being coupled in series with said first current limiter between said fourth and fifth terminals and said sixth terminal being adapted to be coupled to the logic switch;
• and
• a current limit control circuit coupled to said first control terminal and for supplying said first control signal.

A memory system comprising:

• a plurality of content addressable memory (CAM) cells arranged into an array, each of said CAM cells further comprising a storage element and a match detection circuit for detecting a match between incoming data and data stored in said storage element, said match detection circuit further comprising:
• a series circuit between a power terminal and a ground terminal, said series circuit including a current sensing amplifier and a logic switch;
• wherein a current flowing through said series circuit is affected by a state of said logic switch;
• and
• wherein said current sensing amplifier detects the current flow and outputs a signal on a data terminal corresponding to the state of said switch circuit.

A circuit for detecting a logical state of a switching circuit, comprising:

• a current sensing amplifier for detecting a current flow state and indicating the current flow state at a data pin, said current sensing amplifier further comprising,
• a first node coupled to a power source;
• a first, second, third, fourth, and fifth transistors, wherein
• said first transistor has a source coupled to the first node and a drain coupled to a second node;
• said second transistor has a source coupled to the first node and a drain coupled to a third node;
• said first and second transistors forming a current mirror between said first and second nodes and between said first and third nodes;
• said third transistor having a source coupled to said first node, a drain coupled to said data pin, and a gate coupled to said third node;
• said fourth transistor having a source coupled to ground, a drain coupled to said data pin, and a gate coupled to the third node;
• and
• said fifth transistor having a source coupled to ground, a drain coupled to said third node, and a gate coupled to a discharge terminal;
• a first current limiter comprising a sixth transistor having a source coupled to said second node, a drain coupled to a fourth node, and a gate coupled to a first control terminal;
• a voltage regulator comprising a seventh transistor having a source coupled to a sense pin, a drain coupled to the fourth node, and a gate coupled to a reference voltage, wherein the sense pin is adapted to be coupled to the switching circuit.