Memory device
AssigneeMentor Graphics Corporation
InventorHarry Haralambos Athanassiadis
Life of this patent
Estimating the term…
Abstract
A memory device includes an array of memory cells. When in use, each cell can store a charge representing a binary digit of data. Data lines are connected to the memory cells. The data lines are connected to both apply a voltage to the cells to store the charge and to receive a voltage from charge stored in the cells to read a binary digit of data. Read lines are connected to the cells to selectively connect the cell to the data line to apply voltage either from the data lines to the cells or from the cells to the data lines. Control lines also connect to the cells to configure the cells to provide a capacitance to which the data lines can apply voltage and to configure the cells to maintain charge stored in the cells by virtue of a power supply.
Claims15
A memory device comprising:
- an array of memory cells, each of which can store, in use, a charge representing a binary digit of data,
- one or more data lines connected to one or more of the cells to apply a voltage to the cell(s) that enables the cell(s) to store the charge and onto which a voltage may be applied by the cell(s) to read the binary digit of data stored in the cell(s);
- one or more read/write lines connected to one or more of the cells for selectively connecting the cell(s) to the data line(s) for the application of the voltage by the data lines to the cell(s) or the application of the voltage by the cell(s) to the data line(s);
- and
- one or more control lines connected to one or more of the cells for controlling the configuration of the cells,
- wherein the cells are arranged such that the control line(s) can configure the cells to provide a capacitance to which the data line(s) can apply the voltage to the cell(s) and to maintain the charge stored by the cell(s) by virtue of a power supply to the cells thereafter.
The memory device of any one of the preceding claims, wherein the memory cell(s) comprise two cross coupled tri-state inverters.
The memory device of any one of the preceding claims, further comprising a control circuit for selectively applying voltages to the control line(s) to control the configuration of the cell(s).
The memory device of any one of the preceding claims, wherein each memory cell can be connected to a pair of data lines.
The memory device of any one of the preceding claims, further comprising one or more match lines connected to one or more of the cells for indicating when a binary digit represented by voltages applied to the data line(s) of a cell corresponds with the binary digit represented by the voltages stored in the cell.
The memory device of claim 10, wherein the cell(s) are each connected to a pair of match lines.
A Content Addressable Memory comprising the memory device of any one of the preceding claims.
A memory cell arranged such that during the writing of data to the cell, the cell has a dynamic structure and during the reading of data from the cell, the cell has a static structure.
A method of operating a memory cell comprising writing data to the cell such that the cell has dynamic characteristic and reading data from the cell such that the cell has static characteristics.
A memory cell comprising two cross-coupled tri-state inverters.
A memory device as described with reference to any of FIGS. 3 to 9 of the accompanying drawings.
Dependencies are inferred from the claim text.