Chip stacks and methods of making same

A method of interconnecting chips having surface contacts comprising:

• forming a generally annular support structure with a plurality of conductor cavities extending between opposite faces of the support structure and aligned with the surface contacts;
• filling the conductor cavities with conductive material such that the conductive material substantially fills the conductor cavities and extends slightly beyond the opposite faces of the support structure;
• placing chips on the support structure such that the surface contacts are adjacent and aligned with the conductor cavities so as to form a stack of the chips and the support structure;
• and
• processing the stack so as to induce the conductive material to connect to the surface contacts.

A chip stack comprising;

• a first chip having a first and second side wherein the first chip includes a first set of contacts formed in a first pattern on the first side;
• a second chip having a first and second side wherein the second chip includes a first set of contacts formed in the first pattern on the first side and a second set of contacts formed in a second pattern on the first side;
• an interconnecting member having a first and a second side and of a selected thickness wherein the interconnecting member defines an opening and a periphery surrounding the opening and wherein the interconnecting member defines a plurality of conductive elements that are arranged about the periphery of the interconnecting member in the first pattern and wherein the first chip is positioned adjacent the first side of the interconnecting member and the second chip is positioned adjacent the second side of the interconnecting member such that the plurality of interconnecting members interconnect the first set of contacts on the first chip and the second set of contacts on the second chip;
• and
• a third chip having a first and second side wherein the third chip includes a first set of contacts formed in the second pattern on the first side and wherein the third chip is positioned within the opening defined by the interconnecting member so as to interposed between the first and second chips and so that the first set of contacts formed on the second pattern of the third chip are positioned adjacent the second set of contacts formed in the second pattern of the second chip so as to be electrically interconnected to the second chip.

A chip stack comprising:

• a first chip having a first and a second side, wherein a first plurality of contacts are formed on the first side in a first pattern and a second plurality of contacts are formed on the first side in a second pattern;
• a second chip having a first and a second side and a selected thickness, wherein the second side of the second chip includes a first plurality of contacts arranged in the first pattern and wherein the second chip is positioned so that the first plurality of contacts on the second chip are aligned with the first plurality of contacts on the first chip;
• a third chip having a first and a second side wherein the third chip includes a first plurality of contacts arranged in the second pattern on the first side wherein the third chip is located proximate the first side of the second chip such that the second chip is interposed between the first and third chips and so that the first plurality of contacts on the third chip are aligned with the second plurality of contacts on the first chip;
• a first set of interconnecting structures having a first length that are interposed between the first plurality of contacts on the first chip and the first plurality of contacts on the second chip so as to interconnect the first plurality of contacts on the first chip and the first plurality of contacts on the second chip;
• and
• a second set of interconnecting structures having a second length that are interposed between the second plurality of contacts on the first chip and the first plurality of contacts on the third chip so as to interconnect the second plurality of contacts on the first chip and the first plurality of contacts on the third chip and wherein the second length of the second set of interconnecting structures is sized so that the second chip can be interposed between the first side of the third chip and the first side of the first chip.