Method and apparatus for maintaining secure and nonsecure data in a shared memory system
AssigneeATI International SRL
InventorsAllen J.C. Porter, Chun Wang, Kevork Kechichian, Gabriel Varga, David Strasser
Life of this patent
Estimating the term…
Abstract
A graphics processor receives a compressed encrypted video stream. The graphics processor decrypts the compressed encrypted video stream and stores a decrypted version (i.e., a decrypted compressed video stream) in a protected portion of an on-chip or off-chip video memory. The graphics processor then permits processors and other bus masters on the graphics processor to access the on-chip video memory, but conditionally limits access to other bus masters that are located off-chip, such as a central processing unit located off-chip and coupled to the graphics processor via a bus.
Claims32
A device comprising:
- a graphics rendering engine;
- and
- a frame buffer memory that is accessible to a user bus, wherein the frame buffer memory has a defined secure area and an unsecure area.
A graphics processing apparatus comprising:
- a frame buffer memory that is accessible to a user bus;
- and
- an encryption module operatively coupled to the frame buffer memory, the encryption module operative to encrypt data passed to the frame buffer memory and decrypting data passing from the frame buffer memory.
An integrated circuit for an electronic system, the integrated circuit comprising:
- a graphics rendering engine;
- a local frame buffer memory coupled to the graphics rendering engine and having a secure area and an unsecure area, the secure area and the unsecure area being accessible by the graphics rendering engine;
- and
- a user bus interface coupled to the graphics rendering engine and to the local frame buffer memory, the user bus interface operative to couple the integrated circuit to a user bus and to provide access of the unsecure area to the user bus.
Dependencies are inferred from the claim text.