Liquid crystal display device and method of driving same

A liquid crystal display device including an active matrix array made up of switching elements provided at each intersection between a plurality of scanning lines and a plurality of signal lines, and driving means for driving said active matrix array, said driving means comprising:

• scanning circuits N in number, N being a positive integer, which receive a start pulse, and which produce pulse signals sequentially shifted by one-half of a clock signal cycle for each scanning circuit;
• pulse width reducing means, which reduce pulse width of the pulse signals produced by said scanning circuits and produce pulses of reduced width;
• and
• third logic gate circuits N×M in number, M being an integer no less than 2, each provided with a first control terminal and a second control terminal, every M adjacent first logic gate circuits being connected together via said first control terminals thereof, which receive a pulse produced by said pulse width reducing means, and every Mth first logic gate circuit being connected together via said second control terminals thereof, which receive one of M kinds of second control signal.

A driving method for a liquid crystal display device including an active matrix array made up of switching elements provided at each intersection between a plurality of scanning lines and a plurality of signal lines, a vertical drive circuit for driving the scanning lines, and a horizontal drive circuit for driving the signal lines, the vertical drive circuit comprising:

• scanning circuits N in number, N being a positive integer, which receive a start pulse, and which produce pulse signals sequentially shifted by one-half of a clock signal cycle for each scanning circuit;
• first logic gate circuits N×M in number, M being an integer no less than 2, each provided with a first control terminal and a second control terminal, every M adjacent first logic gate circuits being connected together via the first control terminals thereof, which receive a signal produced by one of the N said scanning circuits, and every Mth first logic gate circuit being connected together via the second control terminals thereof, which receive one of M kinds of second control signal;
• and
• second logic gate circuits, each of which receives an output from one of the first logic gate circuits and, via a third control terminal, one of two kinds of third control signal;
• said driving method comprising the steps of:
• (a) inputting to the scanning circuits of the vertical drive circuit a start pulse having a pulse width of 2×M×T, T being a scanning line selection period, and, using a clock signal having a cycle of 2×M×T, causing the respective scanning circuits to produce pulse signals sequentially shifted by one-half cycle of the clock signal for each scanning circuit;
• (b) inputting to the first control terminals of the respective first logic gate circuits the pulse signals sequentially shifted by one-half cycle each, and inputting to the second control terminal of each first logic gate circuit one of M kinds of second control signal having a cycle of M×T and a pulse width of T, thereby causing each first logic gate circuit to produce two pulses of pulse width T, produced (M−1)×T apart from each other;
• (c) inputting to each second logic gate circuit the two pulses produced by one of the first logic gate circuits and one of two kinds of third control signal having a cycle of 2×M×T and a pulse width of M×T, each third control signal being the inverse of the other, thereby causing the respective second logic gate circuits to produce signals having a pulse width of T;
• and
• (d) sequentially inputting the respective signals of pulse width T to the scanning lines.

A driving method for a liquid crystal display device including an active matrix array made up of switching elements provided at each intersection between a plurality of scanning lines and a plurality of signal lines, a vertical drive circuit for driving the scanning lines, and a horizontal drive circuit for driving the signal lines, the vertical drive circuit comprising:

• scanning circuits N in number, N being a positive integer, which receive a start pulse, and which produce pulse signals sequentially shifted by one-half of a clock signal cycle for each scanning circuit;
• pulse width reducing means, which reduce pulse width of the pulse signals produced by the scanning circuits and produce pulses of reduced width;
• and
• third logic gate circuits N×M in number, M being an integer no less than 2, each provided with a first control terminal and a second control terminal, every M adjacent first logic gate circuits being connected together via the first control terminals thereof, which receive a pulse produced by the pulse width reducing means, and every Mth first logic gate circuit being connected together via the second control terminals thereof, which receive one of M kinds of second control signal;
• said driving method comprising the steps of:
• (a) inputting to the scanning circuits of the vertical drive circuit a start pulse having a pulse width of 2×M×T, T being a scanning line selection period, and, using a clock signal having a cycle of 2×M×T, causing the respective scanning circuits to produce pulse signals sequentially shifted by one-half cycle of the clock signal each;
• (b) inputting the respective pulse signals sequentially shifted by one-half cycle each to the pulse width reducing means, thereby producing pulses having respective pulse widths of M×T;
• (c) inputting the respective pulses produced by the pulse width reducing means to the first control terminals of the respective third logic gate circuits, and inputting to the second control terminal of each third logic gate circuit one of M kinds of second control signal having a cycle of M×T and a pulse width of T, thereby causing the respective third logic gate circuits to produce signals having a pulse width of T;
• and
• (d) sequentially inputting the respective signals of pulse width T to the scanning lines.

A driving method for a liquid crystal display device including an active matrix array made up of switching elements provided at each intersection between a plurality of scanning lines and a plurality of signal lines, a vertical drive circuit for driving the scanning lines, and a horizontal drive circuit for driving the signal lines, the vertical drive circuit comprising:

• scanning circuits 2N in number, N being a positive integer, which receive a start pulse, and which produce pulse signals sequentially shifted by one-half of a clock signal cycle for each scanning circuit;
• and
• sixth logic gate circuits N×M in number, M being an integer no less than 2, each provided with a first control terminal and a second control terminal, every M adjacent sixth logic gate circuits being connected together via the first control terminals thereof, which receive signals produced by every other scanning circuit of the 2N scanning circuits, and every Mth sixth logic gate circuit being connected together via the second control terminals thereof, which receive one of M kinds of second control signal;
• said driving method comprising the steps of:
• (a) inputting to the scanning circuits of the vertical drive circuit a start pulse having a pulse width of M×T, T being a scanning line selection period, and, using a clock signal having a cycle of M×T, causing the respective scanning circuits to produce pulse signals sequentially shifted by one-half cycle of the clock signal each;
• (b) inputting to the first control terminals of the respective sixth logic gate circuits signals, sequentially shifted by one cycle each, produced by every other scanning circuit of the 2N scanning circuits, and inputting to the second control terminal of each sixth logic gate circuit one of M kinds of second control signal having a cycle of M×T and a pulse width of T, thereby causing the respective sixth logic gate circuits to produce signals having a pulse width of T;
• and
• (d) sequentially inputting the respective signals of pulse width T to the scanning lines.

A driving method for a liquid crystal display device including an active matrix array made up of switching elements provided at each intersection between a plurality of scanning lines and a plurality of signal lines, a vertical drive circuit for driving the scanning lines, and a horizontal drive circuit for driving the signal lines, the vertical drive circuit comprising:

• scanning circuits N in number, N being a positive integer, which receive a start pulse, and which produce pulse signals sequentially shifted by one-half of a clock signal cycle for each scanning circuit;
• first logic gate circuits N×M in number, M being an integer no less than 2, each provided with a first control terminal and a second control terminal, every M adjacent first logic gate circuits being connected together via the first control terminals thereof, which receive a signal produced by one of the N scanning circuits, and every Mth first logic gate circuit being connected together via the second control terminals thereof, which receive one of M kinds of second control signal;
• and
• second logic gate circuits, each of which receives an output from one of the first logic gate circuits and, via a third control terminal, one of two kinds of third control signal;
• said driving method comprising the steps of:
• (a) inputting to the scanning circuits of the vertical drive circuit a start pulse having a pulse width of M×T, T being a scanning line selection period, and, using a clock signal having a cycle of M×T, causing the respective scanning circuits to produce pulse signals sequentially shifted by one-half cycle of the clock signal each;
• (b) inputting to the first control terminals of the respective first logic gate circuits the pulse signals sequentially shifted by one-half cycle each, and inputting to the second control terminals of M/2 out of every M adjacent first logic gate circuits a second control signal having a cycle of (M/2)×T, thereby causing every other first logic gate circuit to produce two pulses of pulse width T, produced ((M/2)−1)×T apart from each other;
• (c) inputting to every other second logic gate circuit the two pulses produced by every other first logic gate circuit, and inputting to each second logic gate circuit a third control signal having a cycle of M×T, thereby causing every other second logic gate circuit to produce a signal having a pulse width of T;
• and
• (d) sequentially inputting the respective signals of pulse width T to every other scanning line.

A driving method for a liquid crystal display device including an active matrix array made up of switching elements provided at each intersection between a plurality of scanning lines and a plurality of signal lines, a vertical drive circuit for driving the scanning lines, and a horizontal drive circuit for driving the signal lines, the vertical drive circuit comprising:

• scanning circuits N in number, N being a positive integer, which receive a start pulse, and which produce pulse signals sequentially shifted by one-half of a clock signal cycle for each scanning circuit;
• first logic gate circuits N×M in number, M being an integer no less than 2, each provided with a first control terminal and a second control terminal, every M adjacent first logic gate circuits being connected together via the first control terminals thereof, which receive a signal produced by one of the N scanning circuits, and every Mth first logic gate circuit being connected together via the second control terminals thereof, which receive one of M kinds of second control signal;
• and
• second logic gate circuits, each of which receives an output from one of the first logic gate circuits and, via a third control terminal, one of two kinds of third control signal;
• said driving method comprising the steps of:
• (a) inputting to the scanning circuits of the vertical drive circuit a start pulse having a pulse width of M×T, T being a scanning line selection period, and, using a clock signal having a cycle of M×T, causing the respective scanning circuits to produce pulse signals sequentially shifted by one-half cycle of the clock signal each;
• (b) inputting to the first control terminals of the respective first logic gate circuits the pulse signals sequentially shifted by one-half cycle each, and inputting to the second control terminals of every M adjacent first logic gate circuits M/2 kinds of second control signal having a cycle of (M/2)×T, thereby causing each first logic gate circuit to produce two pulses of pulse width T, produced ((M/2)−1)×T apart from each other, each pair of adjacent first logic gate circuits producing pulses having the same phase;
• (c) inputting to the respective second logic gate circuits the two pulses produced by the respective first logic gate circuits, and a third control signal having a cycle of M×T, thereby causing each second logic gate circuit to produce a signal having a pulse width of T, each pair of adjacent second logic gate circuits producing pulses having the same phase;
• and
• (d) sequentially inputting the respective signals of pulse width T to two scanning lines each.

A driving method for a liquid crystal display device including an active matrix array made up of switching elements provided at each intersection between a plurality of scanning lines and a plurality of signal lines, a vertical drive circuit for driving the scanning lines, and a horizontal drive circuit for driving the signal lines, the vertical drive circuit comprising:

• scanning circuits N in number, N being a positive integer, which receive a start pulse, and which produce pulse signals sequentially shifted by one-half of a clock signal cycle for each scanning circuit;
• pulse width reducing means, which reduce pulse width of the pulse signals produced by the scanning circuits and produce pulses of reduced width;
• and
• third logic gate circuits N×M in number, M being an integer no less than 2, each provided with a first control terminal and a second control terminal, every M adjacent first logic gate circuits being connected together via the first control terminals thereof, which receive a pulse produced by the pulse width reducing means, and every Mth first logic gate circuit being connected together via the second control terminals thereof, which receive one of M kinds of second control signal;
• said driving method comprising the steps of:
• (a) inputting to the scanning circuits of the vertical drive circuit a start pulse having a pulse width of M×T, T being a scanning line selection period, and, using a clock signal having a cycle of M×T, causing the respective scanning circuits to produce pulse signals sequentially shifted by one-half cycle of the clock signal each;
• (b) inputting to the pulse reducing means the pulse signals sequentially shifted by one-half cycle each, thereby causing the pulse width reducing means to produce pulses having a pulse width of M×T/2;
• (c) inputting the respective pulses produced by the pulse width reducing means to the first control terminals of the respective third logic gate circuits, and inputting to the second control terminals of M/2 out of every M adjacent third logic gate circuits a second control signal having a cycle of M×T/2, thereby causing every other third logic gate circuit to produce signals having a pulse width of T;
• and
• (d) inputting the respective signals of pulse width T to every other scanning line.

A driving method for a liquid crystal display device including an active matrix array made up of switching elements provided at each intersection between a plurality of scanning lines and a plurality of signal lines, a vertical drive circuit for driving the scanning lines, and a horizontal drive circuit for driving the signal lines, the vertical drive circuit comprising:

• scanning circuits N in number, N being a positive integer, which receive a start pulse, and which produce pulse signals sequentially shifted by one-half of a clock signal cycle for each scanning circuit;
• pulse width reducing means, which reduce pulse width of the pulse signals produced by the scanning circuits and produce pulses of reduced width;
• and
• third logic gate circuits N×M in number, M being an integer no less than 2, each provided with a first control terminal and a second control terminal, every M adjacent first logic gate circuits being connected together via the first control terminals thereof, which receive a pulse produced by the pulse width reducing means, and every Nth first logic gate circuit being connected together via the second control terminals thereof, which receive one of M kinds of second control signal;
• said driving method comprising the steps of:
• (a) inputting to the scanning circuits of the vertical drive circuit a start pulse having a pulse width of M×T, T being a scanning line selection period, and, using a clock signal having a cycle of M×T, causing the respective scanning circuits to produce pulse signals sequentially shifted by one-half cycle of the clock signal each;
• (b) inputting to the pulse reducing means the pulse signals sequentially shifted by one-half cycle each, thereby causing the pulse width reducing means to produce pulses having a pulse width of M×T/2;
• (c) inputting the respective pulses produced by the pulse width reducing means to the first control terminals of the respective third logic gate circuits, and inputting to the second control terminals of every M adjacent third logic gate circuits M/2 kinds of second control signal having a cycle of M×T/2, thereby causing the respective third logic gate circuits to produce signals having a pulse width of T, each pair of adjacent third logic gate circuits producing signals having the same phase;
• and
• (d) sequentially inputting the respective signals of pulse width T to two scanning lines each.

A driving method for a liquid crystal display device including an active matrix array made up of switching elements provided at each intersection between a plurality of scanning lines and a plurality of signal lines, a vertical drive circuit for driving the scanning lines, and a horizontal drive circuit for driving the signal lines, the vertical drive circuit comprising:

• scanning circuits 2N in number, N being a positive integer, which receive a start pulse, and which produce pulse signals sequentially shifted by one-half of a clock signal cycle for each scanning circuit;
• and
• sixth logic gate circuits N×M in number, M being an integer no less than 2, each provided with a first control terminal and a second control terminal, every M adjacent sixth logic gate circuits being connected together via the first control terminals thereof, which receive signals produced by every other scanning circuit of the 2N scanning circuits, and every Mth sixth logic gate circuit being connected together via the second control terminals thereof, which receive one of M kinds of second control signal;
• said driving method comprising the steps of:
• (a) inputting to the scanning circuits of the vertical drive circuit a start pulse having a pulse width of M×T, T being a scanning line selection period, and, using a clock signal having a cycle of M×T, causing the respective scanning circuits to produce pulse signals sequentially shifted by one-half cycle of the clock signal each;
• (b) inputting to the first control terminals of the respective sixth logic gate circuits signals, sequentially shifted by one cycle each, produced by every other scanning circuit of the 2N scanning circuits, and inputting to the second control terminals of M/2 out of every M adjacent sixth logic gate circuits a second control signal having a cycle of M×T/2, thereby causing every other sixth logic gate circuit to produce signals having a pulse width of T;
• and
• (d) sequentially inputting the respective signals of pulse width T to every other scanning line.

A driving method for a liquid crystal display device including an active matrix array made up of switching elements provided at each intersection between a plurality of scanning lines and a plurality of signal lines, a vertical drive circuit for driving the scanning lines, and a horizontal drive circuit for driving the signal lines, the vertical drive circuit comprising:

• scanning circuits 2N in number, N being a positive integer, which receive a start pulse, and which produce pulse signals sequentially shifted by one-half of a clock signal cycle for each scanning circuit;
• and
• sixth logic gate circuits N×M in number, M being an integer no less than 2, each provided with a first control terminal and a second control terminal, every M adjacent sixth logic gate circuits being connected together via the first control terminals thereof, which receive signals produced by every other scanning circuit of the 2N scanning circuits, and every Mth sixth logic gate circuit being connected together via the second control terminals thereof, which receive one of M kinds of second control signal;
• said driving method comprising the steps of:
• (a) inputting to the scanning circuits of the vertical drive circuit a start pulse having a pulse width of M×T, T being a scanning line selection period, and, using a clock signal having a cycle of M×T, causing the respective scanning circuits to produce pulse signals sequentially shifted by one-half cycle of the clock signal each;
• (b) inputting to the first control terminals of the respective sixth logic gate circuits signals, sequentially shifted by one cycle each, produced by every other scanning circuit of the 2N scanning circuits, and inputting to the second control terminals of every M adjacent sixth logic gate circuits M/2 kinds of second control signal having a cycle of M×T/2, thereby causing the respective sixth logic gate circuits to produce signals having a pulse width of T, each pair of adjacent third logic gate circuits producing signals having the same phase;
• and
• (c) sequentially inputting the respective signals of pulse width T to two scanning lines each.

A driving method for a liquid crystal display device including an active matrix array made up of switching elements provided at each intersection between a plurality of scanning lines and a plurality of signal lines, a vertical drive circuit for driving the scanning lines, and a horizontal drive circuit for driving the signal lines, the horizontal drive circuit comprising:

• scanning circuits N in number, N being a positive integer, which receive a start pulse, and which produce pulse signals sequentially shifted by one-half of a clock signal cycle for each scanning circuit;
• first logic gate circuits N×M in number, M being an integer no less than 2, each provided with a first control terminal and a second control terminal, every M adjacent first logic gate circuits being connected together via the first control terminals thereof, which receive a signal produced by one of the N scanning circuits, and every Mth first logic gate circuit being connected together via the second control terminals thereof, which receive one of M kinds of second control signal;
• second logic gate circuits, each of which receives an output from one of the first logic gate circuits and, via a third control terminal, one of two kinds of third control signal;
• and
• sample holding switches;
• said driving method comprising the steps of:
• (a) inputting to the scanning circuits of the horizontal drive circuit a start pulse having a pulse width of 2×M×T, T being a period for sampling J signal lines (J≧1), and, using a clock signal having a cycle of 2×M×T, causing the respective scanning circuits to produce pulse signals sequentially shifted by one-half cycle of the clock signal each;
• (b) inputting to the first control terminals of the respective first logic gate circuits the pulse signals sequentially shifted by one-half cycle each, and inputting to the second control terminals of the respective first logic gate circuits M kinds of second control signal made up of pulses of pulse width T occurring (M−1)×T apart from each other, thereby causing each first logic gate circuit to produce two pulses of pulse width T, produced (M−1)×T apart from each other;
• (c) inputting to each second logic gate circuit the two pulses produced by one of the first logic gate circuits and one of two kinds of third control signal having a cycle of 2×M×T and a pulse width of M×T, each third control signal being the inverse of the other, thereby causing the respective second logic gate circuits to produce signals having a pulse width of T;
• and
• (d) sequentially inputting the respective signals of pulse width T to the sample holding switches.

A driving method for a liquid crystal display device including an active matrix array made up of switching elements provided at each intersection between a plurality of scanning lines and a plurality of signal lines, a vertical drive circuit for driving the scanning lines, and a horizontal drive circuit for driving the signal lines, the horizontal drive circuit comprising:

• scanning circuits N in number, N being a positive integer, which receive a start pulse, and which produce pulse signals sequentially shifted by one-half of a clock signal cycle for each scanning circuit;
• pulse width reducing means, which reduce pulse width of the pulse signals produced by the scanning circuits and produce pulses of reduced width;
• third logic gate circuits N×M in number, M being an integer no less than 2, each provided with a first control terminal and a second control terminal, every M adjacent first logic gate circuits being connected together via the first control terminals thereof, which receive a pulse produced by the pulse width reducing means, and every Mth first logic gate circuit being connected together via the second control terminals thereof, which receive one of M kinds of second control signal;
• and
• sample holding switches;
• said driving method comprising the steps of:
• (a) inputting to the scanning circuits of the horizontal drive circuit a start pulse having a pulse width of 2×M×T, T being a period for sampling J signal lines (J≧1), and, using a clock signal having a cycle of 2×M×T, causing the respective scanning circuits to produce pulse signals sequentially shifted by one-half cycle of the clock signal each;
• (b) inputting the respective pulse signals sequentially shifted by one-half cycle each to the pulse width reducing means, thereby producing pulses having respective pulse widths of M×T;
• (c) inputting the respective pulses produced by the pulse width reducing means to the first control terminals of the respective third logic gate circuits, and inputting to the second control terminal of each third logic gate circuit one of M kinds of second control signal having a cycle of M×T and a pulse width of T, thereby causing the respective third logic gate circuits to produce signals having a pulse width of T;
• and
• (d) sequentially inputting the respective signals of pulse width T to the sample holding switches.

A driving method for a liquid crystal display device including an active matrix array made up of switching elements provided at each intersection between a plurality of scanning lines and a plurality of signal lines, a vertical drive circuit for driving the scanning lines, and a horizontal drive circuit for driving the signal lines, the horizontal drive circuit comprising:

• scanning circuits 2N in number, N being a positive integer, which receive a start pulse, and which produce pulse signals sequentially shifted by one-half of a clock signal cycle for each scanning circuit;
• sixth logic gate circuits N×M in number, M being an integer no less than 2, each provided with a first control terminal and a second control terminal, every M adjacent sixth logic gate circuits being connected together via the first control terminals thereof, which receive signals produced by every other scanning circuit of the 2N scanning circuits, and every Mth sixth logic gate circuit being connected together via the second control terminals thereof, which receive one of M kinds of second control signal;
• and
• sample holding switches;
• said driving method comprising the steps of:
• (a) inputting to the scanning circuits of the horizontal drive circuit a start pulse having a pulse width of M×T, T being a period for sampling J signal lines (J≧1), and, using a clock signal having a cycle of M×T, causing the respective scanning circuits to produce pulse signals sequentially shifted by one-half cycle of the clock signal each;
• (b) inputting to the first control terminals of the respective sixth logic gate circuits signals, sequentially shifted by one cycle each, produced by every other scanning circuit of the 2N scanning circuits, and inputting to the second control terminal of each sixth logic gate circuit one of M kinds of second control signal having a cycle of M×T and a pulse width of T, thereby causing the respective sixth logic gate circuits to produce signals having a pulse width of T;
• and
• (d) sequentially inputting the respective signals of pulse width T to the sampling switches.