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US 2002/0163459 A1Published application
D/A conversion circuit and semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorShou Nagao
Life of this patent
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Abstract
A DAC whose area is held down and a semiconductor device using the DAC are fabricated. A D/A conversion circuit is disclosed, including n resistors A0, A1, . . . An−1, n resistors B0, B1, . . . , Bn−1, two power-supply voltage lines, a power-supply voltage line L and a power-supply voltage line H, maintained at potentials different from each other, n switches SWa0, SWa1, . . . , SWan−1, n switches SWb0, SWb1, . . . , SWbn−1, and an output line, wherein, by n-bit digital signals inputted from the outside, said n switches SWa0, SWa1, . . . , SWan−1 and said n switches SWb0, SWb1, . . . , SWbn−1 are controlled, and, from the output line, an analog gradation voltage signal is outputted.
Claims32
A D/A conversion circuit comprising:
- n resistors A0, A1, . . . An−1,
- n resistors B0, B1, . . . , Bn−1,
- a power-supply voltage line L and a power-supply voltage line H being maintained at potentials different from each other,
- n switches SWa0, SWa1, . . . , SWan−1,
- n switches SWb0, SWb1, . . . , SWbn−1, and
- an output line,
- wherein resistance values of the n resistors A0, A1, . . . An−1 are R, 2R, . . . ,2n−1R, respectively,
- wherein n stands for a natural number of 1 or greater, and R stands for a positive number, respectively,
- wherein resistance values of the n resistors B0, B1, . . . , Bn−1 are R, 2R, . . . ,2n−1R, respectively,
- wherein both ends of each of the n resistors A0, A1, . . . An−1 are connected to one end of each of the n switches SWa0, SWa1, . . . , SWan−1 and to the output line,
- wherein an end of each of the n switches SWa0, SWa1, . . . , SWan−1 which is not connected to each of the n resistors A0, A1, . . . An−1 is connected to the power-supply voltage line L,
- wherein both ends of each of the n resistors B0, B1, . . . , Bn−1 are connected to one end of each of the n switches SWb0, SWb1, . . . , SWbn−1 and to the output line,
- wherein an end of each of the n switches SWb0, SWb1, . . . , SWbn−1 which is not connected to each of the n resistors B0, B1, . . . , Bn−1 is connected to the power-supply voltage line H,
- wherein the n switches SWa0, SWa1, . . . , SWan−1 and the n switches SWb0, SWb1, . . . , SWbn−1 are controlled by n-bit digital signals inputted from the outside,
- wherein inverted signals of the n-bit digital signals which are inputted to the n switches SWa0, SWa1, . . . , SWan−1 are respectively inputted to the n switches SWb0, SWb1, . . . , SWbn−1, and
- wherein an analog gradation voltage signal is outputted from said output line.
13 more elements
A D/A conversion circuit comprising
- a power-supply voltage line H and a power-supply voltage line L being maintained at potentials different from each other,
- n switches SWa0, SWa1, . . . , SWan−1 each including a thin film transistor,
- n switches SWb0, SWb1, . . . , SWbn−1 each including a thin film transistor, and
- an output line,
- wherein the thin film transistor includes,
- a gate electrode,
- an active layer having a source region, a drain region and a channel forming region, and
- a gate insulating film being provided between the gate electrode and the active layer,
- wherein the thin film transistor has resistance value of an internal resistance represented by the general expression, 2n−1R,
- wherein n stands for a natural number of 1 or greater, and R stands for a positive number,
- wherein one end of each of the n switches SWa0, SWa1, . . . , SWan−1 is connected the power-supply voltage line L, while the other is connected to the output line,
- wherein one end of each of said n switches SWb0, SWb1, . . . , SWbn−1 is connected the power-supply voltage line H, while the other is connected to the output line,
- wherein the n switches SWa0, SWa1, . . . , SWan−1 and the n switches SWb0, SWb1, . . . , SWbn−1 are controlled by the n-bit digital signals inputted from the outside,
- wherein inverted signals of the n-bit digital signals inputted to the n switches SWa0, SWa1, . . . , SWan−1 are respectively inputted to the n switches SWb0, SWb1, . . . , SWbn−1, and
- wherein an analog gradation voltage signal is outputted from the output line.
12 more elements
A D/A conversion circuit comprising
- n resistors A0, A1, . . . An−1,
- n resistors B0, B1, . . . , Bn−1,
- a power-supply voltage line L and a power-supply voltage line H being maintained at potentials different from each other,
- n switches SWa0, SWa1, . . . , SWan−1,
- n switches SWb0, SWb1, . . . , SWbn−1, and
- an output line,
- wherein resistance values of the n resistors A0, A1, . . . An−1 are R, 2R, . . . , 2n−1R, respectively,
- wherein n stands for a natural number of 1 or greater, and R stands for a positive number, respectively,
- wherein resistance values of the n resistors B0, B1, . . . , Bn−1 are R, 2R, . . . ,2N−1R, respectively,
- wherein both ends of each of the n resistors A0, A1, . . . An−1 are connected to one end of each of the n switches SWa0, SWa1, . . . , SWan−1 and to the power-supply voltage line L,
- wherein an end of each of the n switches SWa0, SWa1, . . . , SWan−1 which is not connected to each of then resistors A0, A1, . . . An−1 is connected to the output line,
- wherein both ends of each of the n resistors B0, B1, . . . , Bn−1 are connected to one end of each of the n switches SWb0, SWb1, . . . , SWbn−1 and to the power-supply voltage line H,
- wherein an end of each of the n switches SWb0, SWb1, . . . , SWbn−1 which is not connected to each of the n resistors B0, B1, . . . , Bn−1 is connected to the output line,
- wherein the n switches SWa0, SWa1, . . . , SWan−1 and the n switches SWb0, SWb1, . . . , SWbn−1 are controlled by the n-bit digital signals inputted from outside,
- wherein inverted signals of the n-bit digital signals which are inputted to the n switches SWb0, SWb1, . . . , SWbn−1 are respectively inputted to the n switches SWb0, SWb1, . . . , SWbn−1, and
- wherein an analog gradation voltage signal is outputted from the output line.
13 more elements
Dependencies are inferred from the claim text.