Device and method for parallel processing implementation of bit-stuffing/unstuffing and NRZI-encoding/decoding

A device that processes data bits to generate Non-Return-to-Zero-Inverted-encoded data comprising:

• a first data storage element having a first plurality of memory addresses capable of storing the data bits;
• and
• a processing circuit, coupled to the first data storage element, that processes in parallel data bits sent from selected ones of the first plurality of memory addresses, to generate Non-Return-to-Zero-Inverted-encoded data.

A data processing device that processes Non-Return-to-Zero-Inverted-encoded data to generate Non-Return-to-Zero-Inverted-decoded data comprising:

• a first data storage element having a first plurality of memory addresses capable of storing the Non-Return-to-Zero-Inverted-encoded data;
• and
• a processing circuit, coupled to the first data storage element, that processes in parallel data bits sent from selected ones of the first plurality of memory addresses, to generate Non-Return-to-Zero-Inverted-decoded data.

The data processing device according to claim the 30 wherein the second plurality of memory addresses comprises a predetermined number N of memory addresses.

A device that processes bit-stuffed data bits to generate raw data comprising:

• a first data storage element having a first plurality of memory addresses that stores the bit-stuffed data;
• and
• a processing circuit coupled to the first data storage element that processes in parallel data bits sent from selected ones of the first plurality of memory addresses to generate raw data.

A method of processing data bits to generate Non-Return-to-Zero-Inverted-encoded data comprising the steps of:

• sending data bits in parallel from selected ones of a first plurality of memory addresses to a processing circuit;
• and
• processing, in parallel, data bits from the selected ones of the first plurality of memory addresses to generate Non-Return-to-Zero-Inverted-encoded data.

A method for processing Non-Return-to-Zero-Inverted-encoded data to generate Non-Return-to-Zero-Inverted-decoded data comprising the steps of:

• sending data bits representing Non-Return-to-Zero-Inverted-encoded data in parallel from selected ones of a first and a second plurality of memory addresses to a processing circuit;
• and
• processing, in parallel, data bits from the selected ones of the first and second plurality of memory addresses to generate Non-Return-to-Zero-Inverted-decoded data.

A method for processing bit-stuffed data to generate raw data comprising the steps of:

• sending a data bits representing bit-stuffed data in parallel from selected ones of a first and a second plurality of memory addresses to a processing circuit;
• and
• processing, in parallel, data bits received from the selected ones of the first and second plurality of memory addresses to generate raw data.