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AssigneeParthus Ireland Limited
InventorsJohn Horan, Cyril Lahuec, Joe Duigan
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A method and a digital circuit for synthesizing an input signal to produce an output signal are provided. The circuit includes a delay unit with a delay input and a delay output, a switch, and a controller. The selectively switch routes the input signal to the delay input whereafter the switch routes the delay output to the delay input. The controller controls the delay unit in response to the input signal and the output signal. A counter is provided to count a predetermined number of times the delay output is routed to the delay input whereafter the input signal is routed to the delay input to trigger the delay input. The digital circuit synthesizes the input signal to define a Delay-Locked loop (DLL) in which the delay unit is a voltage controlled delay line (VCDL). The invention extends to a computer program product executing the method and to an embedded circuit including the digital circuit.
A digital circuit for synthesizing an input signal to produce an output signal, the circuit including:
A method of synthesizing an input signal, the method including:
An embedded circuit which includes a delay-locked loop for synthesizing an output signal from an input signal, the delay-locked loop including:
A computer program product stored in a medium readable by a computer, the medium including instructions which, when read by the computer, cause the computer to:
A machine-readable medium storing a description of a circuit, said circuit including:
Dependencies are inferred from the claim text.