Operation amplification circuit, constant voltage circuit and reference voltage circuit

An operation amplification circuit, comprising:

• a differential amplification circuit that receives a differential signal and performs a differential amplification thereof;
• an output amplification circuit that amplifies an output of the differential amplification circuit;
• and
• a bias circuit that determines a bias of the differential amplification circuit and the output amplification circuit, the bias circuit including a reference voltage circuit that generates a specified reference voltage, the reference voltage circuit including a first MOS transistor and a second MOS transistor of an identical conduction type serially connected to one another, the first MOS transistor including a gate electrode that is formed from polysilicon including an N-type impurity and connected to a drain electrode thereof, the second MOS transistor including a gate electrode that is formed from polysilicon including a P-type impurity and connected to a source electrode thereof, a voltage corresponding to a difference between threshold voltages of the first and second MOS transistors being generated at a common connection section of the first and second MOS transistors as the reference voltage.

A reference voltage circuit comprising:

• an enhancement type MOS transistor of a first conduction type, the enhancement type MOS transistor including a gate electrode and a drain electrode, the gate electrode of the enhancement type MOS transistor including an impurity of the second conduction type;
• a depletion type MOS transistor of the first conduction type serially connected to the enhancement type MOS transistor of the first conduction type, the depletion type MOS transistor including a gate electrode and a source electrode, the gate electrode of the depletion type MOS transistor including an impurity of the first conduction type;
• a first power supply line that supplies a first potential is connected to the gate electrode and the source electrode of the depletion type MOS transistor;
• a second power supply line that supplies a second potential lower than the first potential is connected to the gate electrode and the drain electrode of the enhancement type MOS transistor;
• and
• an output terminal provided at a connection point of the drain electrode of the depletion type MOS transistor and the source electrode of the enhancement type MOS transistor.