US 2002/0163379 A1 · CMOS reference voltage circuit

Abstract

A CMOS reference voltage circuit, preferably formed on a semiconductor integrated circuit, and outputting a reference voltage having a temperature-independent characteristic, comprises first and second diode-connected transistors (or diodes), respectively grounded and driven with two constant currents bearing a constant current ratio to each other, and a unit for amplifying a differential voltage of output voltages from the first and second transistors by a preset factor and for summing the amplified differential voltage to an output voltage of the first or second transistor. The amplifying and summing unit is formed by two OTAs 11, 12 and a current mirror circuit 13. The first OTA 11 is fed with the differential voltage and the second OTA 12 has a reverse phase input terminal fed with an output voltage from the first or second transistor and a forward phase input terminal connected to its output terminal and driven with a current proportional to an output current of the first OTA 11, with an output terminal voltage of the second OTA 12 being used as an output voltage.

Claims27

Dependent claims

A CMOS reference voltage circuit for generating and outputting a reference voltage, including:

first and second diode-connected transistors, respectively grounded and driven by two constant currents with a constant current ratio;
and
means for amplifying a differential voltage between output voltages of said first and second diode-connected transistors by a predetermined factor and summing a resulting amplified voltage to an output voltage of said first or second diode-connected transistor, in which
said means for amplifying and summing comprises:
first and second operational transconductance amplifiers (OTAs);
and
a current mirror circuit, wherein
said first OTA receives said differential voltage;
and
said second OTA has a first input terminal for receiving an output voltage from said first or second diode-connected transistor and has a second input terminal connected to an output terminal of said second OTA and driven with a current proportional to an output current of said first OTA, an output terminal voltage of said second OTA being said reference voltage.

7 more elements

A CMOS reference voltage circuit for generating and outputting a reference voltage, including:

first and second diode-connected transistors, respectively grounded and driven by two constant currents with a constant current ratio;
and
means for amplifying a differential voltage between output voltages of said first and second diode-connected transistors by a predetermined factor and summing a resulting amplified voltage to an output voltage of said first or second diode-connected transistor, in which
said means for amplifying and summing is comprised of two differential pairs,
one of the differential transistors of a second one of said differential pairs receiving an output voltage of the first or second diode-connected transistors, the other differential transistor being diode-connected and being driven with a current proportional to an output current of one of the transistors of the first differential pair;
said first differential pair and the second differential pair being driven with two constant currents having a constant current ratio to each other;
an operating input voltage range of said second differential pair being a predetermined number multiple of the operating input voltage range of said first differential pair to produce a desired amplification factor.

4 more elements

A reference voltage circuit, comprising

first and second emitter-grounded bipolar transistors, each having a base connected to a collector, with each collector being fed with a constant current;
first and second operational conductance amplifiers (OTAs), each having at least a first input terminal and a second input terminal and adapted for outputting from an output terminal a current proportional to a differential voltage between voltages applied to said first and second input terminals;
and
a current mirror circuit having at least an input end and an output end, with the ratio of the current fed to said input end to the current output from the output end being of a predetermined value, wherein
the collectors of the first and second bipolar transistors are connected respectively to the first and second input terminals of the first OTA;
said output terminal of said first OTA is connected to said input end of said current mirror circuit;
the output terminal of said second OTA and said collector of said second bipolar transistor are respectively connected to the first and second input terminals of said second OTA;
and
a connection node of said first input terminal and the output terminal of said second OTA are connected to said output end of said current mirror circuit, said output terminal of said second OTA outputting a reference voltage.

6 more elements

A reference voltage circuit comprising

first and second bipolar transistors, each having a emitter grounded and having a base connected to a collector, with each collector being fed with a constant current;
a first differential pair comprised of a pair of MOS transistors, having sources connected in common and driven with a constant current and having gates for receiving differentially base-to-emitter voltages of said first and second bipolar transistors;
a current mirror circuit having an input end and plural (K2) number of output ends, said current mirror circuit receiving from said input end an output current of said first differential pair and outputting output currents proportional to the input current at said plural (K2) number of output ends;
a second differential pair comprised of a pair of MOS transistors, having sources connected in common and driven with a constant current, one of the MOS transistors having a gate fed with a base-to-emitter voltage of said second bipolar transistor and the other MOS transistor having a gate connected to a drain and connected to the first output end of said current mirror circuit;
and
third to number (K2+1) differential pairs, each comprised of a pair of MOS transistors, having sources connected in common and driven with a constant current, one MOS transistor of said differential pair having a gate connected to a gate of a MOS transistor of a preceding stage differential pair having a drain connected to a gate, the other MOS transistor of said differential pair having a drain connected to a gate and connected to a corresponding output end of the current mirror circuit;
a reference voltage being taken out at a drain of the MOS transistor of the number (K2+1) differential pair having the drain and the gate connected together.

4 more elements

A reference voltage circuit comprising

first and second bipolar transistors, each having a emitter grounded and having a base connected to a collector, with each collector being fed with a constant current;
a first differential pair comprised of a pair of MOS transistors, having sources connected in common driven with a constant current and having gates for receiving differentially base-to-emitter voltages of said first and second bipolar transistors;
a first current mirror circuit having an input end and an output end, said first current mirror circuit receiving from said input end an output current of said first differential pair and outputting output currents proportional to the input current at said output end;
a second current mirror circuit having an input end and plural (K2) number of output ends, said second current mirror circuit receiving from said input end a constant current from a constant current source and outputting output currents proportional to the input constant current at said K2 output ends;
a second differential pair comprised of a pair of MOS transistors, having sources connected in common driven with a constant current, one of the MOS transistors having a gate fed with a base-to-emitter voltage of said second bipolar transistor and the other MOS transistor having a gate connected to a drain and connected to the first output end of said current mirror circuit;
third to number K2 differential pairs, each comprised of a pair of MOS transistors, having sources connected in common driven with a constant current, each MOS transistor having a drain and a gate connected together, one MOS transistor of said differential pair, having a drain connected to a drain of the other MOS transistor of a preceding stage differential pair, said other MOS transistor having a drain and a gate connected together, said drain of said one MOS transistor being connected to the corresponding output end of the second current mirror circuit,
the other MOS transistor of said differential pair, having a drain connected to a drain of one MOS transistor of a subsequent stage differential pair, said one MOS transistor having a drain and a gate connected together, said drain of the other MOS transistor being connected to a corresponding output end of said second current mirror circuit;
and
a number (K2+1) differential pair, each comprised of a pair of MOS transistors, having sources connected in common driven with a constant current, each MOS transistor having a drain and a gate connected together, the drain of one of the MOS transistors being connected to the drain of the other MOS transistor of the number K2 differential pair having a drain and a gate connected together, said drain being connected to said output end of said first current mirror circuit, a reference voltage being taken out at the drain of the other MOS transistor as an output terminal.

6 more elements

A reference voltage circuit including a differential amplifier circuit, said differential amplifier circuit comprising:

a differential pair comprised of first and second MOS transistors, having sources connected in common and driven with a constant current;
and
a first current mirror circuit comprised of third and fourth MOS transistors, connected to the drains of the first and second MOS transistors of said differential pair, said third and fourth MOS transistors acting as active loads, wherein
the gate W/L ratio of each of said first and second MOS transistors is 1:K2, with K2 being an integer larger than 1,
the gate W/L ratio of each of said third and fourth MOS transistors is K3:1, with K3 being an integer larger than 1;
or
the gate W/L ratio of said first and second MOS transistors is K2:1, with the gate W/L ratio of said third and fourth MOS transistors being 1:K3;
and
there is provided a bipolar transistor, having an emitter grounded and having a base and a collector connected together with the collector fed with a constant current;
the collector of said bipolar transistor being connected to the gate of said first MOS transistor, a drain and a gate of the second MOS transistor being connected together, a reference voltage being taken out from the drain of said second MOS transistor as an output terminal.

7 more elements

A reference voltage circuit including a differential amplifier circuit, said differential amplifier circuit comprising:

a differential pair comprised of first and second MOS transistors, having sources connected in common and driven with a constant current;
a first current mirror circuit comprised of third and fourth MOS transistors, connected respectively to the drains of the first and second MOS transistors of said differential pair, said third and fourth MOS transistors acting as active load;
and
a fifth MOS transistor arranged in a source follower configuration, having a gate connected to the drain of the second MOS transistor and driven with a constant current, wherein
the gate W/L ratio of said first and second MOS transistors is 1:K2, where K2 being an integer larger than 1, with the gate W/L ratio of said third and fourth MOS transistors being K3:1, where K3 being an integer larger than 1;
or
the gate W/L ratio of said first and second MOS transistors is K2:1, with the gate W/L ratio of said third and fourth MOS transistors being 1:K3;
a source of said fifth MOS transistor is an output terminal;
said output terminal being connected to the gate of said second MOS transistor of said differential pair to form a voltage follower;
and
there being provided a bipolar transistor, having an emitter grounded and having a base and a collector connected together, with the collector being driven with a constant current;
the collector of said bipolar transistor being connected to the gate of said first MOS transistor of said differential pair;
a reference voltage being taken out at said output terminal.

10 more elements

Dependencies are inferred from the claim text.

CMOS reference voltage circuit

Life of this patent

CMOS reference voltage circuit

Life of this patent

Abstract

Claims27