US 2002/0163372 A1 · METHOD AND APPARATUS FOR LATCHING A CLOCKED DATA SIGNAL

Abstract

A latch includes memory and pulldown circuitry coupled to nodes of the memory for pulling one of the nodes down responsive to data. The pulldown circuitry has gating circuitry for gating the pulling down responsive to a clock signal. The latch also has pull up circuitry coupled to the other one of the memory nodes. A first pull up circuitry section is operable to pull the other one of the memory nodes up to a high state responsive to data. The first pull up circuitry section includes second gating circuitry. The second gating circuitry is operable to gate the pulling up of the other one of the memory nodes responsive to a pull up circuitry clock signal. The first pull up circuitry section more quickly pulls up its memory node, so that the two nodes are pulled up and down at more nearly the same time.

Claims20

Dependent claims

A latch comprising:

a memory having a first node for storing a high or low state, and a second node for storing a complement to the state;
pulldown circuitry coupled to the first memory node for pulling the first node down to the low state responsive to a data signal received by the pulldown circuitry, wherein the pulldown circuitry includes first gating circuitry coupled to a pulldown circuitry clock signal node for timing the pulling down of the first memory node;
and
pull up circuitry having a first pull up circuitry section coupled to the second memory node for pulling the second memory node up to a high state responsive to a data signal received at the first pull up circuitry section, wherein the first pull up circuitry section includes second gating circuitry coupled to a pull up circuitry clock signal node for timing the pulling up of the second memory node.

1 more element

Latch circuitry comprising:

a memory having a first node for storing a state and a second node for storing a complement to the first node state;
deasserting circuitry coupled to the first memory node for deasserting the first memory node state responsive to a data signal received by the deasserting circuitry, wherein the deasserting circuitry has first gating circuitry coupled to a deasserting circuitry clock signal node for timing the deasserting;
and
first asserting circuitry having a first asserting circuitry section coupled to the second memory node for asserting the second memory node state responsive to a data signal received by the asserting circuitry, wherein the asserting circuitry section has second gating circuitry coupled to an asserting circuitry clock signal node for gating the asserting.

1 more element

A method for latching a clocked data signal comprising the steps of:

deasserting, by deasserting circuitry of a first latch, a state of a first memory node of the latch responsive to a deasserting circuitry data signal, wherein the deasserting is timed by first gating circuitry of the deasserting circuitry responsive to a deasserting circuitry clock signal;
and
asserting, by a first asserting circuitry section of first asserting circuitry of the first latch, a complementary state of a second memory node of the first latch responsive to a first asserting circuitry section data signal, wherein the asserting is timed by second gating circuitry of the first asserting circuitry section responsive to an asserting circuitry clock signal.

Dependencies are inferred from the claim text.

Method and apparatus for latching a clocked data signal

Life of this patent

Method and apparatus for latching a clocked data signal

Life of this patent

Abstract

Claims20