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US 2002/0163367 A1Published application
Clock supply bias circuit and single-phase clock drive frequency dividing circuit using the same
AssigneeNEC Corporation
InventorGlenn Keiji Murata
Life of this patent
Estimating the term…
Abstract
A single-phase clock CLK0 is divided into a clock signal CLK1 to drive nMOS transistor and a clock signal CLK2 to drive pMOS transistor, and the resulting clock signals are inputted to DFF circuits 1 to 3 constituting a frequency dividing circuit, making gms of nMOS and pMOS transistors larger than that could be achieved using the conventional technique. Therefore, frequency dividing performance can be greatly improved in comparison with that achieved using conventional technology.
Claims7
A clock supply bias circuit comprising:
- a clock input terminal for receiving a single-phase clock as an input signal and clock output terminals for outputting said input signal as a first clock and a second clock,
- said first clock and said second clock being constructed such that said first clock and said second clock have the same phase as that of said single-phase clock and have different voltages, respectively.
A frequency dividing circuit driven by single-phase clock, comprising:
- a first DFF circuit, a second DFF circuit and a third DFF circuit each consisting of a MOS transistor, a NOR circuit, a NAND circuit, an output buffer circuit and a clock supply bias circuit, all of said circuits being connected in parallel with each other between a positive power supply and a negative power supply, and said first DFF circuit, said second DFF circuit and said third DFF circuit further being constructed such that all of said DFF circuits are driven by clocks supplied by said clock supply bias circuit,
- said clock supply bias circuit further comprising:
- a clock input terminal;
- a first capacitor connected in series to said positive power supply via a first current control element and disposed between said clock input terminal and said positive power supply;
- a second capacitor connected in series to said negative power supply via a second current control element and disposed between said clock input terminal and said negative power supply;
- a first resistor connected in parallel with said first capacitor;
- a second resistor connected in parallel with said second capacitor;
- and
- a diode connected in parallel with said first capacitor and said second capacitor being connected in series, said clock supply bias circuit further being constructed such that an anode of said diode serves as a first clock output line and a cathode of said diode serves as a second clock output line,
- said first DFF circuit, said second DFF circuit and said third DFF circuit being further constructed such that all of said DFF circuits consist of the same circuit configuration and each of said DFF circuits further comprises:
- a first pMOS transistor having a source connected to said positive power supply, a drain connected to a drain of a first nMOS transistor and a gate of a second pMOS transistor, and a gate connected to a data input signal line and a gate of a second nMOS transistor;
- said first nMOS transistor having a source connected to a drain of said second nMOS transistor, and a gate connected to a gate of a third nMOS transistor and said first clock output line;
- said second pMOS transistor having a source connected to said positive power supply, and a drain connected to a drain of said third nMOS transistor and a gate of a fourth nMOS transistor;
- said second nMOS transistor having a source connected to said negative power supply;
- said third pMOS transistor having a source connected to said positive power supply, a drain connected to a drain of said fourth nMOS transistor and an output signal line, and a gate connected to said second clock output line;
- said third nMOS transistor having a source connected to said negative power supply;
- and
- said fourth nMOS transistor having a source connected to said negative power supply,
- said NOR circuit comprising:
- a fourth pMOS transistor having a source connected to said positive power supply, a drain connected to a drain of a fifth nMOS transistor, a drain of a sixth nMOS transistor and said data input signal line of said first DFF circuit, and a gate connected to a gate of said sixth nMOS transistor and said output signal line of said third DFF circuit;
- said fifth nMOS transistor having a gate connected to a signal input terminal, and a source connected to said negative power supply;
- and
- said sixth nMOS transistor having a source connected to said negative power supply,
- said NAND circuit comprising:
- a fifth pMOS transistor having a source connected to said positive power supply, a drain connected to a drain of a seventh nMOS transistor and said data input signal line of said second DFF circuit, and a gate connected to a gate of said seventh nMOS transistor and said output signal line of said third DFF circuit;
- said seventh nMOS transistor having a source connected to a drain of an eighth nMOS transistor;
- and
- said eighth nMOS transistor having a source connected to said negative power supply, and a gate connected to said output signal line of said first DFF circuit,
- said output buffer circuit comprising:
- a sixth pMOS transistor having a source connected to said positive power supply, a drain connected to a drain of a ninth nMOS transistor, a gate of a seventh pMOS transistor, a gate of a tenth nMOS transistor and said second output signal terminal, and a gate connected to a gate of said ninth nMOS transistor, said output signal line of said second DFF circuit and said data input signal line of said third DFF circuit;
- said ninth nMOS transistor having a source connected to said negative power supply;
- said seventh pMOS transistor having a drain connected to a drain of said tenth nMOS transistor and said first output signal terminal;
- and
- said tenth nMOS transistor having a source connected to said negative power supply.
31 more elements
Dependencies are inferred from the claim text.