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US 2002/0163358 A1Published application
Use of dangling partial lines for interfacing in a PLD
AssigneeAltera Corporation
InventorsBrian D. Johnson, Andy L. Lee, Cameron McClintock, Giles V. Powell, Paul Leventis
Life of this patent
Estimating the term…
Abstract
A routing structure in a PLD is implemented in a staggered fashion. Routing lines that would otherwise be “partial” and dangling at a routing architecture boundary are driven, providing additional flexibility for routing signals to the PLD core from the boundaries.
Claims22
A programmable logic device (PLD), comprising:
- a plurality of logic elements (LE's) arranged in an array;
- a signal routing architecture including a plurality of signal routing lines to route signals among the LE's;
- and
- a plurality of signal drivers along each of the signal routing lines,
- wherein
- for each of the signal routing lines,
- that signal routing line has an integer N associated with the signal routing line;
- the drivers along that signal routing line are regularly spaced along that signal routing line at an interval of N LE's for that line;
- for each of a first set of at least some of the signal routing lines,
- that signal routing line is substantially interrupted by an interface region such that a partial signal routing line is formed for that signal routing line between the interface region and a driver along the signal routing line from the interface region less than N LE's from the interface region;
- and
- the PLD further comprises an input driver configured to drive from the interface region along the partial signal routing line formed for that signal routing line.
9 more elements
A programmable logic device (PLD), comprising:
- a plurality of logic elements (LE's) arranged in an array;
- a signal routing architecture including a plurality of signal routing lines to route signals among the LE's;
- and
- a plurality of signal drivers along each of the signal routing lines,
- wherein,
- for each of the signal routing lines,
- that signal routing line has an integer N associated with the signal routing line;
- and
- the drivers along that signal routing line are regularly spaced along that signal routing line at an interval of N LE's for that line;
- and
- for each of a first set of at least some of the signal routing lines,
- that signal routing line is substantially interrupted by an interface region such that a partial signal routing line is formed for that signal routing line between the interface region and a driver along the signal routing line from the interface region less than N LE's from the interface region.
9 more elements
A programmable logic device (PLD), comprising:
- a plurality of logic elements (LE's) arranged in an array;
- a signal routing architecture including a plurality of signal routing lines;
- and
- a plurality of signal drivers along each of the signal routing lines,
- wherein,
- for each of a set of the signal routing lines,
- that signal routing line has an integer N associated with the signal routing line;
- the drivers along that signal routing line are regularly spaced along that signal routing line at an interval of N LE's for that line;
- and
- the drivers along each signal routing line of the set are staggered with respect to the drivers along an adjacent signal routing line of the set.
7 more elements
A method of configuring a design of a programmable logic device (PLD), comprising:
- a) configuring the design such that the PLD includes a plurality of logic elements (LE's) arranged in an array;
- b) configuring the design such that the PLD includes a signal routing architecture including a plurality of signal routing lines to route signals among the LE's;
- and
- c) configuring the design such that the PLD includes a plurality of signal drivers along each of the signal routing lines,
- including,
- for each of the signal routing lines,
- associating an integer N with the signal routing line;
- and
- configuring the design such that the drivers of the PLD along that signal routing line are regularly spaced along that signal routing line at an interval of N LE's for that line;
- and
- for each of a first set of at least some of the signal routing lines,
- configuring the design such that the signal routing line of the PLD is substantially interrupted by an interface region such that a partial signal routing line is formed for that signal routing line between the interface region and a driver along the signal routing line from the interface region less than N LE's from the interface region;
- and
- configuring the design such that the PLD further comprises an input driver configured to drive from the interface region along the partial signal routing line formed for that signal routing line.
11 more elements
A method of configuring a design of a programmable logic device (PLD), comprising:
- configuring the design such that the PLD includes a plurality of logic elements (LE's) arranged in an array;
- configuring the design such that the PLD includes a signal routing architecture including a plurality of signal routing lines to route signals among the LE's;
- and
- a plurality of signal drivers along each of the signal routing lines,
- wherein,
- for each of the signal routing lines,
- that signal routing line has an integer N associated with the signal routing line;
- and
- the method includes configuring the design such that the drivers along that signal routing line are regularly spaced along that signal routing line at an interval of N LE's for that line;
- for each of a first set of at least some of the signal routing lines,
- the method includes configuring the design such that that signal routing line is substantially interrupted by an interface region such that a partial signal routing line is formed for that signal routing line between the interface region and a driver along the signal routing line from the interface region less than N LE's from the interface region.
8 more elements
A method of configuring the design of a programmable logic device (PLD), comprising:
- configuring the design such that the PLD includes a plurality of logic elements (LE's) arranged in an array;
- configuring the design such that the PLD includes a signal routing architecture including a plurality of signal routing lines;
- and
- configuring the design such that a plurality of signal drivers along each of the signal routing lines,
- wherein,
- the method includes configuring the design such that, for each of a set of the signal routing lines,
- that signal routing line has an integer N associated with the signal routing line;
- the drivers along that signal routing line are regularly spaced along that signal routing line at an interval of N LE's for that line;
- and
- the drivers along each signal routing line of the set are staggered with respect to the drivers along an adjacent signal routing line of the set.
7 more elements
Dependencies are inferred from the claim text.