Architecture and interconnect scheme for programmable logic circuits

A programmable logic circuit comprising:

• a plurality of logic clusters, each of said logic clusters having a plurality of programmably interconnected cells for performing logic functions on logic signals;
• a set of intraconnection matrix routing lines coupling a set of said plurality of logic clusters;
• a plurality of logic blocks, each of said logic blocks having a plurality of programmably interconnected cells for performing logic functions on logic signals;
• a first set of bi-directionally programmable access lines coupling a first set of said plurality of logic blocks.

In a programmable logic circuit having a plurality of cells for performing logic functions on logic signals, a method of forming complex logic functions for programmably coupling a group of said cells by routing signals from one of said cells to another of said cells, said method comprising the steps of:

• programmably interconnecting a plurality of said cells to form a first logic cluster, a second logic cluster, and a third logic cluster via a set of intraconnection matrix routing lines;
• programmably conducting a signal corresponding to a first set of intraconnection matrix routing lines of a first logic cluster to a first set of intraconnection matrix routing lines of said second logic cluster via a first set of bi-directionally programmable access lines;
• programmably interconnecting a plurality of said cells to form a first logic block, a second logic block, and a third logic block;
• programmably conducting a signal corresponding to a first set of bi-directionally programmable access lines of a first logic block to a first set of bi-directionally programmable access lines of said second logic block via a first level of interconnections.

A field programmable gate array comprising:

• a plurality of cells for performing logic functions on signals input to said field programmable gate array;
• an intraconnection matrix for programmably interconnecting a plurality of said cells to form a logic cluster;
• a plurality of programmable switches connectable between two adjacent said intraconnection matrices to form logic cluster extensions;
• a plurality of block connectors together with said logic clusters, said intraconnection matrices, and said extensions to form a logic block;
• a plurality of programmable switches connectable between two adjacent said logic blocks to form logic block extensions;
• a first level of programmable interconnections for interconnecting a plurality of logic blocks to form a block cluster;
• a second level of programmable interconnections for interconnecting a plurality of block clusters to form a block sector;
• a first set of programmable switches connecting a plurality of logic blocks to said first level of programmable interconnections;
• a second set of programmable switches connecting a plurality of logic blocks to said second level of programmable interconnections;