Dynamic register with IDDQ testing capability
AssigneeBroadcom Corporation
InventorMehdi Hatamian
Life of this patent
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Abstract
The present invention is a method and a system for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating voltage during a steady state of a clock signal. The circuit includes a transmission gate which has input and output terminals, and operates in response to a clock signal. The node is located proximal to the output terminal of the transmission gate. The method includes the operations of driving the node with an input signal when the transmission gate is open during a first steady state of the clock signal and pulling the node to a fixed voltage when the transmission gate is closed during a second steady state of the clock signal.
Claims24
A method for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating voltage, the circuit including a transmission gate operating in response to a clock signal, the transmission gate having an input terminal and an output terminal, the node being located proximal to the output terminal of the transmission gate, the method comprising the operations of:
- driving the node with an input signal when the transmission gate is open during a first steady state of the clock signal and allows the input signal to pass from the input terminal to the output terminal;
- and
- pulling the node to a fixed voltage when the transmission gate is closed during a second steady state of the clock signal and prevents the input signal from passing through.
A system for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating voltage, the circuit including a transmission gate operating in response to a clock signal, the transmission gate having an input terminal and an output terminal, the node being located proximal to the output terminal of the transmission gate, the system comprising:
- a control circuit coupled to the circuit at the node, the control circuit not controlling the voltage at the node when the transmission gate is open during a first steady state of the clock signal and pulling the node to a fixed voltage when the transmission gate is closed during a second steady state of the clock signal.
Dependencies are inferred from the claim text.