Apparatus and method for testing fuses

A circuit for testing fuses in an integrated circuit comprising:

• a bank of control resistors electrically interposed between a first supply node and a second supply node;
• a testing circuit having an input and an access to a reference in the testing circuit, wherein the input of the testing circuit is in electrical communication with the first supply node;
• and
• wherein the bank of control resistors comprises a plurality of elements connected in parallel and electrically interposed between a first node and the second supply node, wherein the second supply node is connected to a potential higher than the first supply node and the first node, and wherein the elements comprise a first switching device connected in series with a control resistor.

A method for determining a desired test time for fuses, the method comprising:

• initializing a reference voltage in a testing circuit;
• applying a pre-charge voltage across a control resistor;
• allowing the pre-charge voltage to decay;
• determining a first time at which the pre-charge voltage has decayed to a value less than the reference voltage in the testing circuit;
• adjusting the reference voltage in the testing circuit to obtain an updated reference voltage;
• applying the pre-charge voltage across the control resistor;
• allowing the pre-charge voltage to decay;
• determining a second time at which the pre-charge voltage has decayed to a value less than the reference voltage in the testing circuit;
• repeating adjusting through determining a second time if the second time is less than the first time;
• and
• selecting the first time as the desired test time.

A method for determining a desired test time for fuses, the method comprising:

• initializing a reference voltage in a testing circuit;
• applying a voltage across a control resistor;
• causing the voltage across the control resistor to charge;
• determining a first time at which the voltage across the control resistor has increased to a value greater than the reference voltage in the testing circuit;
• adjusting the reference voltage in the testing circuit to obtain an updated reference voltage;
• applying a voltage across the control resistor;
• causing the voltage across the control resistor to charge;
• determining a second time at which the voltage across the control resistor has increased to a value greater than the reference voltage in the testing circuit;
• repeating adjusting through determining a second time if the second time is less than the first time;
• and
• selecting the first time as the desired test time.

A method for determining a desired test time for a fuse, comprising:

• initializing a reference voltage in a testing circuit;
• applying a pre-charge voltage across the control resistor;
• determining the time at which the pre-charge voltage decays to a value less than the reference voltage in the testing circuit;
• adjusting the reference voltage if the determined decay time is greater than a preselected desired decay time;
• repeating applying a pre-charge voltage through adjusting the reference voltage so long as the reference voltage was adjusted;
• and
• selecting the determined decay time as the test time.

A method for determining a desired test time for a fuse, comprising:

• initializing a reference voltage in a testing circuit;
• applying a pre-charge voltage across the control resistor;
• determining the time at which the pre-charge voltage charges to a value greater than the reference voltage in the testing circuit;
• adjusting the reference voltage if the determined charge time is greater than a preselected desired charge time;
• repeating applying a pre-charge voltage through adjusting the reference voltage so long as the reference voltage was adjusted;
• and
• selecting the determined charge time as the test time.

A circuit for testing fuses in an integrated circuit comprising:

• at least one bank of at least one fuse electrically interposed between a first supply node and a second supply node;
• and
• a testing circuit having an input and an access to a reference in the testing circuit,
• wherein the input of the testing circuit is in electrical communication with the first supply node.

A circuit for testing fuses, comprising:

• a bank of control resistors electrically interposed between a first supply node and a second supply node;
• a testing circuit comprising a comparator having an input and an access to a reference in the testing circuit, wherein the input of the testing circuit is in electrical communication with the first supply node;
• wherein the bank of control resistors comprises a plurality of elements connected in parallel and electrically interposed between a first node and the second supply node, and wherein the elements comprise a first switching device connected in series with a fuse;
• and
• a second switching device electrically interposed between the first supply node and the first node.

A circuit for testing fuses, comprising:

• a bank of control resistors electrically interposed between a first supply node and a second supply node;
• a testing circuit comprising a comparator having first and second inputs, wherein the first input of the testing circuit is in electrical communication with the first supply node;
• a variable reference voltage source electrically connected to the second input of the comparator;
• wherein the bank of control resistors comprises a plurality of elements connected in parallel and electrically interposed between a first node and the second supply node, and wherein the elements comprise a first switching device connected in series with a fuse;
• and
• a second switching device electrically interposed between the first supply node and the first node.

A integrated circuit, comprising:

• an array of memory cells;
• and
• an electric circuit, electrically connected to the array of memory cells, the electric circuit comprising:
• a bank of control resistors electrically interposed between a first supply node and a second supply node;
• and
• a testing circuit having an input and an access to a reference in the testing circuit, wherein the input of the testing circuit is in electrical communication with the first supply node.

A computer system having a memory, comprising:

• an electric circuit electrically connected to the memory, the electric circuit comprising:
• a bank of control resistors electrically interposed between a first supply node and a second supply node;
• and
• a testing circuit having an input and an access to a reference in the testing circuit, wherein the input of the testing circuit is in electrical communication with the first supply node.

A computer system having a memory, comprising:

• an electric circuit electrically connected to the memory, the electric circuit comprising:
• a bank of selectable control resistors electrically interposed between a first supply node and a second supply node;
• and
• a testing circuit having an input and an access to a reference in the testing circuit, wherein the input of the testing circuit is in electrical communication with the first supply node.

A computer system having a memory, comprising:

• an electric circuit electrically connected to the memory, the electric circuit comprising:
• a bank of control resistors electrically interposed between a first supply node and a second supply node;
• a testing circuit having an input and an access to a reference in the testing circuit,
• wherein the input of the testing circuit is in electrical communication with the first supply node;
• and
• wherein the bank of control resistors comprises a plurality of elements connected in parallel and electrically interposed between a first node and the second supply node, wherein the second supply node is connected to a potential higher than the first supply node and the first node, and wherein the elements comprise a first switching device connected in series with a control resistor.

A computer system having a first electrical circuit and a second electrical circuit connected to the first electrical circuit, the second electrical circuit comprising:

• at least one bank of at least one fuse electrically interposed between a first supply node and a second supply node;
• and
• a testing circuit having an input and an access to a reference in the testing circuit,
• wherein the input of the testing circuit is in electrical communication with the first supply node.

A computer system having a first electrical circuit and a second electrical circuit connected to the first electrical circuit, the second electrical circuit comprising:

• a bank of control resistors electrically interposed between a first supply node and a second supply node;
• a testing circuit comprising a comparator having an input and an access to a reference in the testing circuit, wherein the input of the testing circuit is in electrical communication with the first supply node;
• wherein the bank of control resistors comprises a plurality of elements connected in parallel and electrically interposed between a first node and the second supply node, and wherein the elements comprise a first switching device connected in series with a fuse;
• and
• a second switching device electrically interposed between the first supply node and the first node.

A computer system having a first electrical circuit and a second electrical circuit connected to the first electrical circuit, the second electrical circuit comprising:

• a bank of control resistors electrically interposed between a first supply node and a second supply node;
• a testing circuit comprising a comparator having first and second inputs, wherein the first input of the testing circuit is in electrical communication with the first supply node;
• a variable reference voltage source electrically connected to the second input of the comparator;
• wherein the bank of control resistors comprises a plurality of elements connected in parallel and electrically interposed between a first node and the second supply node, and wherein the elements comprise a first switching device connected in series with a fuse;
• and
• a second switching device electrically interposed between the first supply node and the first node.