Method for forming an interconnect structure with air gap compatible with unlanded vias

A semiconductor interconnect structure, comprising:

• a first level conductive structure having a top surface and a side surface, the side surface having an lower portion surrounded by first level air gaps and an upper portion surrounded by a first cap layer;
• an etching stop layer over the first cap layer;
• and
• an opening disposed over the top surface and part of the upper portion of the side surface of the first level conductive structure, wherein the first level air gaps are isolated from the opening by the first cap layer.

A semiconductor interconnect structure, comprising:

• a first level conductive structure on a substrate;
• a first cap layer over the first level conductive structure;
• an etching stop layer over the first cap layer;
• and
• an opening having a lower portion that exposes the top surface of the first level conductive structure at a first point, the lower portion also exposes part of the first cap layer at a second point, and exposes part of the etching stop layer at a third point.

A semiconductor interconnect structure, comprising:

• a first level conductive structure on a substrate, wherein sidewalls of the first level conductive structure are surrounded by a first level air gap;
• a first cap layer over the first level conductive structure;
• an etching stop layer over the first cap layer;
• and
• an opening exposing part of a surface of the first level conductive structure, the opening also exposing part of the first cap layer and part of the etching stop layer, wherein the first level air gap is isolated from the opening by the first cap layer.

A semiconductor interconnect structure, comprising:

• a first level conductive structure on a substrate;
• a first cap layer on the first level conductive structure;
• a side dielectric layer on sidewalls of the first level conductive structure and at least part of sidewalls of the first cap layer;
• a second cap layer over the first cap layer;
• an etching stop layer over the second cap layer;
• and
• an opening disposed over part of a surface of the first level conductive structure, over part of the first cap layer, over part of the side dielectric layer, and over part of the second cap layer, wherein the first level conductive structure is surrounded by first level air gaps, wherein the first level air gaps are isolated from the opening by the side dielectric layer and the second cap layer.

A semiconductor interconnect structure, comprising:

• a first level conductive structure on a substrate, wherein sidewalls of the first level conductive structure are surrounded by first level air gaps;
• a first cap layer over the first level conductive structure;
• a side dielectric layer disposed between the first level conductive structure, the second cap layer and the first level air gap;
• a second cap layer over the first cap layer;
• an etching stop layer over the second cap layer;
• and
• an opening penetrating through the etching stop layer, a portion of the second cap layer, a portion of the first cap layer to expose a portion of the first level conductive structure, a portion of the side dielectric layer, wherein the first level air gaps are isolated from the opening by the side dielectric layer.

A semiconductor interconnect structure, comprising:

• a first level conductive structure on a substrate;
• a first cap layer over the first level conductive structure;
• a side dielectric layer on sidewalls of the first level conductive structure and at least part of the first cap layer;
• a second cap layer over the first cap layer;
• an etching stop layer over the second cap layer;
• and
• an opening penetrating through the etching stop layer, the second cap layer, the first cap layer to expose a portion of the first level conductive structure, a portion of the side dielectric layer, wherein
• sidewalls of the side dielectric layer are surrounded by first level air gaps and the first level air gaps are isolated from the opening by the side dielectric layer.

A method for forming an interconnect structure, comprising:

• providing a substrate;
• forming a sacrificial layer on the substrate;
• forming a sacrificial dielectric layer on the sacrificial layer, wherein the sacrificial dielectric layer has a thickness;
• patterning the sacrificial layer and the sacrificial dielectric layer to form an opening exposing the substrate;
• forming a conductive structure filling the opening;
• removing the sacrificial dielectric layer to expose the sacrificial layer;
• forming a conformal capping layer over the substrate to cover the conductive structure and the sacrificial layer;
• performing a consumption process to remove the sacrificial layer, so as to form an air gap surrounding the conductive structure;
• forming a conformal etching stop layer on the conformal capping layer;
• forming a second dielectric layer on the etching stop layer;
• patterning the second dielectric layer, the conformal etching stop layer, and the conformal capping layer to form an opening that exposes a portion of the conductive layer but not the air gap;
• and
• forming a plug filling the opening.