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US 2002/0163080 A1Published application
Semiconductor device and its manufacture
AssigneeFujitsu Limited
InventorsToshio Taniguchi, Taiji Ema, Toru Anezaki
Life of this patent
Estimating the term…
Abstract
In a logic area, impurities are doped into the gate electrode and the source/drain diffusion regions of a MIS transistor. Thereafter in a memory cell area, word lines are patterned, source/drain regions are formed, and contact holes are formed. Side wall spacers of the MIS transistor in the logic area are made of silicon oxide. A semiconductor device of logic-memory can be manufactured by a reduced number of manufacture processes while the transistor characteristics are stabilized and the fine patterns in the memory cell are ensured.
Claims40
A semiconductor device comprising:
- a semiconductor substrate;
- a memory cell area and a logic area defined in said semiconductor substrate;
- word lines formed in said memory cell area, said word line including a gate electrode;
- gate electrodes of complementary transistors formed in said logic area;
- a first insulating layer formed on an upper surface of said word line in said memory area and on side walls of said gate electrode in said logic area;
- and
- a second insulating layer covering side walls of said word line in said memory area and covering said gate electrode in said logic area.
4 more elements
A semiconductor device comprising:
- a semiconductor substrate;
- a memory cell area and a logic area defined in said semiconductor substrate;
- word lines formed in said memory area, said word line including a gate electrode;
- gate electrodes of complementary transistors formed in said logic area;
- a first insulating layer formed on said word line in said memory area, said first insulating layer having substantially a same pattern as said word line;
- a second insulating layer formed on side walls of said gate electrode in said logic area, said second insulating layer being made of a same composition as said first insulating layer;
- and
- a third insulating layer formed on an upper surface of said gate electrode in said logic area, said third insulating layer being made of the same composition as said first insulating layer,
- wherein a thickness of said first insulating layer is equal to a sum of thicknesses of said second and third insulating layers.
6 more elements
A semiconductor device comprising:
- a semiconductor substrate;
- a memory cell area and a logic area defined in said semiconductor substrate;
- word lines formed in said memory area, said word line including a gate electrode;
- gate electrodes of complementary transistors formed in said logic area;
- side wall spacers made of silicon nitride and formed on side walls of said word line in said memory cell area;
- and
- side wall spacers made of silicon oxide and formed on side walls of said gate electrode in said logic area.
4 more elements
A method of manufacturing a semiconductor device comprising the steps of:
- forming a first conductive film on a gate insulating film formed in first and second areas of a semiconductor substrate;
- selectively removing the first conductive film to form a gate electrode of a first MIS transistor in the first area and a conductive pattern covering a whole surface of the second area;
- forming side wall spacer insulating films made of a first insulating film on side walls of the gate electrode of the first MIS transistor;
- by using the gate electrode of the first MIS transistor as a mask, introducing impurities into the first area to form source/drain diffusion regions of the first MIS transistor;
- forming a second insulating film over the semiconductor substrate including the first and second areas;
- selectively removing the second insulting film and the first conductive film to form a lamination pattern of a gate electrode of a second MIS transistor in the second area;
- by using the lamination pattern as a mask, introducing impurities into the second area to form source/drain diffusion regions of the second MIS transistor;
- forming side wall spacer insulating films made of a third insulating film on side walls of the lamination pattern;
- and
- forming a second conductive film connecting at least one of the source/drain diffusion regions in the second area.
7 more elements
A method of manufacturing a semiconductor device comprising the steps of:
- (a) forming a first conductive film on a gate insulating film formed in first and second areas of a semiconductor substrate;
- (b) selectively removing the first conductive film to form a gate electrode of a first MIS transistor in the first area and a conductive pattern covering a whole surface of the second area;
- (c) forming side wall spacer insulating films made of a first insulating film on side walls of the gate electrode of the first MIS transistor;
- (d) by using the gate electrode of the first MIS transistor as a mask, introducing impurities into the first area to form source/drain diffusion regions of the first MIS transistor and also into the gate electrode and the conductive pattern;
- (e) selectively forming a metal silicide film on the source/drain regions and the gate electrode of the first MIS transistor and on the conductive pattern;
- (f) forming a second insulating film over the semiconductor substrate including the first and second areas;
- (g) selectively removing the second insulting film and the first conductive film to form a lamination pattern of a gate electrode of a second MIS transistor in the second area;
- (h) by using the lamination pattern as a mask, introducing impurities into the second area to form source/drain diffusion regions of the second MIS transistor;
- (i) forming side wall spacer insulating films made of a third insulating film on side walls of the lamination pattern;
- and
- (j) forming a second conductive film connected to at least one of the source/drain diffusion regions in the second area.
8 more elements
A method of manufacturing a semiconductor device, comprising the steps of:
- forming a plurality of word lines in a memory cell area of a semiconductor substrate, the word line having a lamination structure of a first conductive film and a first insulating film;
- by using the lamination structure as a mask, introducing impurities into the semiconductor substrate to form source/drain regions;
- forming first side wall spacer insulating films on side walls of the lamination structure, the first side wall spacer insulating film having substantially a same etching characteristic as the first insulating film;
- forming a second insulating film on the memory cell area, the second insulating film having an etching characteristic different from the first insulating film;
- selectively etching the second insulating film on one of the source/drain regions on both sides of the word line in the memory cell area to form a first contact hole defined by the first side wall spacer insulating film;
- filling an inside of the first contact hole with a second conductive film;
- forming a third conductive film and a third insulating film on the second insulating film to cover the second conductive film filled in the first contact hole, the third insulating film having an etching characteristic different from the second insulating film, and patterning the third insulating film and the third conductive film to form a bit line electrically connected to said one of the source/drain regions via the second conductive film;
- forming second side wall spacer insulating films on side walls of the bit line made of the third insulating film and the third conductive film, the second side wall insulating film having an etching characteristic different from the second insulating film;
- forming a fourth insulating film on the second insulating film, to cover the bit line, the fourth insulating film having substantially a same etching characteristic as the second insulating film;
- selectively and sequentially etching the fourth and second insulating films above the other of the source/drain regions opposing to said one source/drain across said word line in the memory cell area, to form a second contact hole defined by the second and first side wall spacer insulating films;
- and
- forming a storage electrode electrically connected to the other of the source/drain regions via the second contact hole.
9 more elements
A method of manufacturing a semiconductor device, comprising the steps of:
- (a) forming element isolation insulating films in first and second areas of a semiconductor substrate to define active regions;
- (b) depositing a first conductive film on a whole surface of the semiconductor substrate;
- (c) forming a first mask member on the first conductive film, the first mask member covering the first area and exposing the second area;
- (d) by using the first mask member as a mask, etching the first conductive film to leave the first conductive film extending in the first area;
- (e) by using the first mask member or the first conductive film as a mask, introducing impurities into the semiconductor substrate in the second area;
- (f) depositing a second conductive film over a whole surface of the semiconductor substrate;
- (g) forming a second mask member on the second conductive film, the second mask member having a pattern of gate electrodes to be formed in the second area;
- (h) by using the second mask member as a mask, etching the second conductive film to form a plurality of second gate electrodes in the second area;
- and
- (i) patterning the first conductive film in the first area to form a plurality of first gate electrodes.
7 more elements
A semiconductor device, comprising:
- a semiconductor substrate including first and second areas;
- a plurality of first conductive patterns formed in the first area;
- a plurality of second conductive patterns formed in the second area, said second conductive pattern having a structure different from said first conductive pattern;
- first, second, third and fourth insulating films formed on said second conductive pattern;
- and
- said third and fourth insulating films formed on the first conductive pattern.
3 more elements
A method of manufacturing a semiconductor device, comprising the steps of:
- (a) forming element isolation insulating films in first and second areas of a semiconductor substrate to define active regions;
- (b) depositing a lamination structure of a first conductive film and a first insulating film on a whole surface of the semiconductor substrate;
- (c) forming a first mask member on the lamination structure, the first mask member having a pattern of a wiring forming area in the second area;
- (d) by using the first mask member as a mask, etching the first insulating film of the lamination structure to leave the first insulating film only in the wiring forming area in the second area;
- (e) removing the first mask member;
- (f) forming a second mask member on the first conductive film in the first area, the second mask member having a pattern of a wiring forming area;
- and
- (g) etching the first conductive film by using as a mask the second mask member and the left first insulating film.
5 more elements
A semiconductor device, comprising:
- a semiconductor substrate having first and second areas and an intermediate area;
- a first gate electrode structure formed in the first area, said first gate electrode structure having a plurality of first conductive patterns;
- a second gate electrode structure formed in the second area, said second gate electrode structure having a lamination structure of a plurality of second conductive patterns having a same structure as said first conductive patterns, and a first insulating film having a same pattern and formed on said second conductive pattern;
- a third gate electrode structure formed of a lamination of a third conductive pattern formed in the intermediate area, said third conductive pattern having a same structure as said first conductive pattern, and a second insulating film formed on a partial surface of said third conductive pattern and having a same structure as said first insulating film;
- and
- an upper insulating film formed on surfaces of said first, second and third gate electrode structures.
3 more elements
Dependencies are inferred from the claim text.