Semiconductor device having LDD-type source/drain regions and fabrication method thereof

A method of fabricating a semiconductor device comprising:

• forming a plurality of first gate patterns and a plurality of second gate patterns on a semiconductor substrate;
• forming first low-concentration source/drain regions on both sides of each of the first gate patterns;
• forming second low-concentration source/drain regions on both sides of each of the second gate patterns;
• conformably forming a first etch stop layer on the substrate having the first and second low-concentration source/drain regions;
• forming spacers over sidewalls of the first and second gate patterns;
• implanting impurity ions into the first low-concentration source/drain regions using the first gate patterns and the spacers over the sidewalls of the first gate patterns as implantation masks, thereby forming first high-concentration source/drain regions having higher-concentration than the first low-concentration source/drain regions;
• implanting impurity ions into the second low-concentration source/drain regions using the second gate patterns and the spacers over the sidewalls of the second gate patterns as implantation masks, thereby forming second high-concentration source/drain regions having higher concentrations than the second low-concentration source/drain regions;
• removing the spacers;
• forming an interlayer insulating layer on the entire surface of the resultant structure where the spacers are removed;
• and
• successively patterning the interlayer insulating layer and the first etch stop layer to form at least one first contact hole and at least one second contact hole, wherein the first contact hole exposes a first LDD-type source/drain region composed of the first low-concentration source/drain region and the first high-concentration source/drain region, and the second contact hole exposes a second LDD-type source/drain region composed of the second low-concentration source/drain region and the second high-concentration source/drain region.

A method of fabricating an SRAM cell having a first contact region and a second contact region, comprising:

• forming an isolation layer within a semiconductor substrate to define active regions therein;
• forming a pair of first gate patterns extending across the active region in the first contact region and a second gate pattern extending across the active region in the second contact region;
• forming first low-concentration source/drain regions on both sides of each of the first gate patterns;
• forming second low-concentration source/drain regions on both sides of the second gate pattern;
• conformably forming a first etch stop layer on the substrate having the first and second low-concentration source/drain regions;
• forming spacers over sidewalls of the first and second gate patterns, the spacers having an etch selectivity with respect to the first etch stop layer;
• implanting impurity ions into the first low-concentration source/drain regions using the first gate patterns and the spacers over the sidewalls of the first gate patterns as implantation masks, thereby forming first high-concentration source/drain regions having higher concentrations than the first low-concentration source/drain regions;
• implanting impurity ions into the second low-concentration source/drain regions using the second gate pattern and the spacer over the sidewalls of the second gate pattern as implantation masks, thereby forming second high concentration source/drain regions having higher concentrations than the second low-concentration source/drain regions;
• removing the spacers;
• forming an interlayer insulating layer on the entire surface of the substrate where the spacers are removed;
• and
• successively patterning the interlayer insulating layer and the first etch stop layer to form a first contact hole between the first gate patterns and a second contact hole in the second contact region, wherein the first contact hole exposes a first LDD-type source/drain region composed of the first low-concentration source/drain region and the first high-concentration source/drain region, and the second contact hole exposes a second LDD-type source/drain region composed of the second low-concentration source/drain region and the second high-concentration source/drain region.

A semiconductor device comprising:

• an insulated gate pattern formed on a semiconductor substrate;
• LDD-type source/drain regions formed in the semiconductor substrate on both sides of the gate pattern;
• a first conformal etch stop layer formed on the substrate having the gate pattern and the LDD-type source/drain regions;
• an interlayer insulating layer formed on the first etch stop layer;
• and
• a contact hole penetrating the interlayer insulating layer and the first etch stop layer, wherein the contact hole exposes the LDD-type source/drain region.

A semiconductor device comprising:

• an insulated gate pattern formed on a semiconductor substrate;
• low-concentration source/drain regions formed in the semiconductor substrate on both sides of the gate pattern;
• high-concentration source/drain regions formed at the low-concentration source/drain regions, the respective high-concentration source/drain regions being spaced apart from the edge of the gate pattern;
• a conformal etch stop layer formed on the resultant structure having the gate pattern, the low-concentration source/drain regions and the high-concentration source/drain regions;
• an interlayer insulating layer formed on the etch stop layer;
• and
• at least one contact hole penetrating the interlayer insulating layer and the etch stop layer, wherein the contact hole exposing an LDD-type source/drain region composed of the low-concentration source/drain region and the high-concentration source/drain region.

A semiconductor device comprising:

• a plurality of first gate patterns and a plurality of second gate patterns formed on a semiconductor substrate;
• first LDD-type source/drain regions formed in the semiconductor substrate on both sides of the first gate patterns;
• second LDD-type source/drain regions formed in the semiconductor substrate on both sides of the second gate patterns;
• a conformal etch stop layer formed on the substrate having the first and second LDD-type source/drain regions;
• an interlayer insulating layer formed on the etch stop layer;
• and
• a first contact hole and a second contact hole that penetrate the interlayer insulating layer and the etch stop layer, the first contact hole exposing the first LDD-type source/drain region and the second contact hole exposing the second LDD-type source/drain region.