Semiconductor device and manufacturing method thereof

A semiconductor device comprising:

• at least a pixel TFT formed in a pixel portion over a substrate;
• and
• at least an n-channel TFT and at least a p-channel TFT in a driver circuit over said substrate;
• each of said pixel TFT, and said n-channel and said p-channel TFT in said driver circuit comprising:
• an active layer having at least a source region, a drain region and a channel forming region;
• a gate electrode adjacent to said active layer with a gate insulating film interposed therebetween,
• wherein at least a part of or a whole of an LDD region of said n-channel TFT in said driver circuit is formed so as to overlap said gate electrode of said n-channel TFT,
• wherein an LDD region of said pixel TFT in said pixel portion is formed so as not to overlap said gate electrode of said pixel TFT, and
• wherein a concentration of an n-type impurity element contained in a vicinity of a boundary between said channel forming region and said LDD region of said n-channel TFT in said driver circuit is lower than that contained in a vicinity of a boundary between said LDD region and said drain region.

A semiconductor device comprising:

• a pixel portion having a pixel TFT over a substrate;
• and
• a driver circuit having at least first n-channel TFT and second n-channel TFT over said substrate, each of said TFT comprising:
• an active layer having at least a source region, a drain region and a channel forming region;
• at least an LDD region formed in said active layer;
• a gate electrode adjacent to said active layer with a gate insulating film interposed therebetween,
• wherein a whole of said LDD region of said first n-channel TFT overlaps said gate electrode thereof, a part of said LDD region of said second n-channel TFT overlaps said gate electrode thereof, and said LDD region of said pixel TFT does not overlap said gate electrode thereof, and
• wherein a concentration of an n-type impurity element contained in said LDD region of said first or second n-channel TFT becomes higher as a distance from said drain region adjoining said LDD region decreases.

A semiconductor device comprising:

• a pixel portion having a pixel TFT over a substrate;
• and
• a driver circuit having at least first n-channel TFT and second n-channel TFT over said substrate, each of said TFT comprising:
• an active layer having at least a source region, a drain region and a channel forming region;
• at least an LDD region formed in said active layer;
• a gate electrode adjacent to said active layer with a gate insulating film interposed therebetween,
• wherein a whole of said LDD region of said first n-channel TFT overlaps said gate electrode thereof, a part of said LDD region of said second n-channel TFT overlaps said gate electrode thereof, and said LDD region of said pixel TFT does not overlap said gate electrode thereof, and
• wherein a concentration of an n-type impurity element contained in a vicinity of a boundary between a channel forming region and said LDD region of said first or second n-channel TFT is lower than that contained in a vicinity of a boundary between said LDD region and a drain region.

A method of manufacturing a semiconductor device having at least a pixel portion and a driving circuit over a same substrate comprising the steps of:

• forming a semiconductor film over said substrate;
• patterning said semiconductor film to form an active layer;
• forming a gate insulating film in contact with said active layer;
• forming a conductive film on said gate insulating film;
• patterning said conductive film to form a gate electrode having a tapered portion;
• introducing an n-type impurity element into a region to be an n-channel TFT of said driver circuit through said tapered portion of said gate electrode to form an n-type impurity region (b) having a concentration gradient of said n-type impurity element in a direction in parallel with said substrate;
• introducing an n-type impurity element to form an n-type impurity region (a);
• introducing a p-type impurity element to form a p-type impurity region (a);
• and
• introducing an n-type impurity element in a self-aligning manner with said gate electrode being as the mask to form an n-type impurity region (c).