Methods of forming gap fill and layers formed thereby

A capacitor stack configuration comprising:

• a substrate;
• a dielectric film having been deposited on an upper surface of said substrate;
• metallic interconnects having been deposited on said dielectric film and extending therefrom, said metallic interconnects forming high aspect ratio gaps therebetween, wherein said high aspect ratio gaps have an aspect ratio from about 7:1 to about 10:1;
• and
• a dielectric fill layer having been deposited over said metallic interconnects and gaps, wherein said dielectric fill layer substantially fills said high aspect ratio gaps without leaving voids.

A semiconductor stack structure comprising:

• a substrate;
• a dielectric film having been deposited on an upper surface of said substrate;
• metallic interconnects having been deposited on said dielectric film and extending therefrom, said metallic interconnects forming high aspect ratio gaps therebetween, wherein a depth of said high aspect ratio gaps is greater than a width of said high aspect ratio gaps;
• and
• a dielectric fill layer having been deposited over said metallic interconnects and gaps, by positioning said substrate, dielectric film and metallic interconnects into a deposition chamber;
• co-injecting an oxidant and water vapor into the deposition chamber;
• and injecting a silicon-containing gas or vapor into the deposition chamber;
• wherein the silicon-containing gas or vapor reacts with the oxidant in the deposition chamber according to a normal temperature process to deposit said dielectric fill layer, wherein said dielectric fill layer substantially fills said high aspect ratio gaps without leaving voids.

A method of forming a dielectric layer on a substrate comprising the steps of:

• co-injecting ozone and water vapor through first channels in a showerhead and into a deposition chamber;
• and
• injecting silane gas or vapor through second channels in the showerhead which are separate from the first channels, and into the deposition chamber;
• wherein the silicon-containing gas or vapor reacts with the oxidant in the deposition chamber according to a normal temperature process to deposit a layer onto the substrate.

A capacitor stack configuration comprising:

• a substrate;
• a dielectric film having been deposited on an upper surface of said substrate;
• metallic interconnects having been deposited on said dielectric film and extending therefrom, said metallic interconnects forming high aspect ratio gaps therebetween, wherein an ratio of said high aspect ratio gaps is in the range of about 7:1 to 10:1;
• and
• a dielectric fill layer having been deposited over said metallic interconnects and gaps, wherein said dielectric fill layer substantially fills said high aspect ratio gaps without leaving voids;
• and wherein said dielectric fill layer having been deposited by positioning said substrate, dielectric film and metallic interconnects into a deposition chamber;
• co-injecting an oxidant and water vapor into the deposition chamber;
• and injecting a silicon-containing gas or vapor into the deposition chamber;
• wherein the silicon-containing gas or vapor reacts with the oxidant in the deposition chamber according to a normal temperature process to deposit said dielectric fill layer.