Mixed metal nitride and boride barrier layers
AssigneeMicron Technology, Inc.
InventorsBrian A. Vaartstra, Donald L. Westmoreland
Life of this patent
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Abstract
Mixed metal aluminum nitride and boride diffusion barriers and electrodes for integrated circuits, particularly for DRAM cell capacitors. Also provided are methods for CVD deposition of MxAlyNzBw alloy diffusion barriers, wherein M is Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, or W; x is greater than zero; y is greater than or equal to zero; the sum of z and w is greater than zero; and wherein when y is zero, z and w are both greater than zero.
Claims91
A semiconductor device comprising:
- a layer having silicon;
- and
- a separate diffusion barrier layer deposited on said silicon layer, said diffusion barrier layer comprising aluminum, a metal selected from the group consisting of Ti, Zr, Hf, V, Nb, Ta, Cr, Mo and W, and at least one element selected from the group consisting of N and B.
A diffusion barrier located between a silicon substrate and a metal film in a semiconductor device, said diffusion barrier comprising;
- a mixed metal boron-nitride layer formed on said film and having the formula MxAlyNzBw, wherein M is Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, or W;
- x is greater than zero;
- y is greater than or equal to zero;
- the sum of z and w is greater than zero;
- and wherein when y is zero, z and w are both greater than zero.
A capacitor, comprising a first conductive layer, a dielectric layer, and a second conductive layer, at least one of said first and second conductive layers having the formula MxAlyNzBw, wherein M is Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, or W;
- x is greater than zero;
- y is greater than or equal to zero;
- the sum of z and w is greater than zero;
- and wherein when y is zero, z and w are both greater than zero.
A capacitor, comprising a dielectric layer, a first conductive layer, a second conductive layer, and a conductive barrier layer containing a material having the formula MxAlyNzBw, wherein M is Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, or W;
- x is greater than zero;
- y is greater than or equal to zero;
- the sum of z and w is greater than zero;
- and wherein when y is zero, z and w are both greater than zero.
An integrated circuit comprising a capacitor, said capacitor comprising a first conductive layer, a dielectric layer, and a second conductive layer, at least one of said first and second conductive layers having the formula MxAlyNzBw, wherein M is Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, or W;
- x is greater than zero;
- y is greater than or equal to zero;
- the sum of z and w is greater than zero;
- and wherein when y is zero, z and w are both greater than zero.
A method for fabricating a capacitor comprising the steps of:
- forming a first conductive layer;
- forming a dielectric layer,
- forming a second conductive layer,
- wherein at least one of said first and second conductive layers is a material having the formula MxAlyBw, wherein M is Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, or W;
- x is greater than zero;
- y is greater than or equal to zero;
- the sum of z and w is greater than zero;
- and wherein when y is zero, z and w are both greater than zero.
A method for fabricating a capacitor having a first and a second electrode, comprising the following steps:
- forming an insulative layer overlying a substrate;
- forming an opening in said insulative layer in order to expose said substrate;
- forming a conductive plug in said opening, said conductive plug forming a first portion of the first electrode of said capacitor, said conductive plug recessed below a surface of said insulative layer;
- forming a first conductive layer, for preventing diffusion of atoms, in said opening and overlying said conductive plug such that said first conductive layer is surrounded on sidewalls by said insulative layer, said first conductive layer forming a second portion of the first electrode, said first conductive layer being formed of a MxAlyNzBw material deposited by chemical vapor deposition;
- forming a second conductive layer overlying said first conductive layer, said second conductive layer forming a third portion of the first electrode, and wherein M is Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, or W;
- x is greater than zero;
- y is greater than or equal to zero;
- the sum of z and w is greater than zero;
- and wherein when y is zero, z and w are both greater than zero.
A chemical vapor deposition method of depositing a single layer comprising a first metal, aluminum, nitrogen and boron on a semiconductor wafer, comprising the steps of:
- placing said semiconductor wafer in a chemical vapor deposition chamber;
- heating said wafer;
- introducing a selected metal precursor, a selected aluminum precursor, a selected nitrogen precursor and a selected boron precursor into said chamber to generally simultaneously deposit said first metal, aluminum, nitrogen and boron on said semiconductor wafer.
A method of depositing an amorphous alloy comprising a first metal, aluminum, nitrogen and boron on an object, comprising the steps of
- placing said object within a chemical vapor deposition chamber;
- and injecting gaseous precursors of said first metal, aluminum, nitrogen and boron into said chamber.
A method of depositing a generally conformal layer comprising a first metal, aluminum, nitrogen and boron on a semiconductor wafer, comprising the steps of:
- providing a chemical vapor deposition reactor;
- placing said wafer within said reactor;
- heating said wafer to a selected processing temperature of from about 250 to about 550° C.;
- establishing a pressure of 100 millitorr to 10 torr within said reactor;
- and
- injecting a selected quantity of a gaseous organometallic precursor into said chamber;
- injecting a selected quantity of an aluminum precursor into said chamber.
Dependencies are inferred from the claim text.