Solid state imaging device, method of manufacturing the same, and solid state imaging system

A method of manufacturing a solid state imaging device, comprising the steps of:

• forming a first buried layer of one conductivity type in an interior of a seventh semiconductor layer of opposite conductivity type by introducing one conductivity type impurity into the seventh semiconductor layer by using a first mask;
• forming a first well region of opposite conductivity type on a surface layer of the seventh semiconductor layer and over the first buried layer by introducing opposite conductivity type impurity into the seventh semiconductor layer by using the first mask;
• forming a one conductivity type region to be connected to the first buried layer and to contain the first well region by introducing one conductivity type impurity into the surface layer of the seventh semiconductor layer;
• forming a second buried layer of opposite conductivity type, that has higher impurity concentration than the seventh semiconductor layer, under the one conductivity type region by introducing opposite conductivity type impurity in an interior of the seventh semiconductor layer by using a second mask;
• forming a second well region of opposite conductivity type, that is connected to the first well region, by introducing opposite conductivity type impurity on a surface layer of the one conductivity type region and over the second buried layer by using the second mask;
• forming a channel doped layer of one conductivity type by introducing one conductivity type impurity on a surface layer of the second well region by using the second mask;
• forming a high concentration buried layer of opposite conductivity type, that has higher impurity concentration than the second well region, in an interior of the second well region under the channel doped layer by introducing opposite conductivity type impurity in an interior of the second well region by using a third mask;
• forming a gate insulating film on the seventh semiconductor layer by a thermal oxidation;
• forming a gate electrode on the gate insulating film to cover the high concentration buried layer and to bring the high concentration buried layer close to a source region side;
• and
• forming a source region and a drain region of one conductivity type on a surface layer of the second well region on both sides of the gate electrode and forming an impurity region on a surface layer of the first well region.

A solid state imaging device comprising:

• a photo diode formed in a second semiconductor layer of opposite conductivity type in a first semiconductor layer of one conductivity type;
• and
• a light signal detecting insulated gate field effect transistor formed in a fourth semiconductor layer of opposite conductivity type in a third semiconductor layer of one conductivity type adjacently to the photo diode;
• wherein a portion of the photo diode comprises an impurity region of one conductivity type on a surface layer of the second semiconductor layer, and a portion of the insulated gate field effect transistor comprises a source region and a drain region of one conductivity type on a surface layer of the fourth semiconductor layer, a channel region between the source region and the drain region, a gate electrode over the channel region via a gate insulating film, and a high concentration buried layer of opposite conductivity type in the fourth semiconductor layer in a neighborhood of the source region under the channel region,
• the first semiconductor layer is connected to the third semiconductor layer, and the second semiconductor layer is connected to the fourth semiconductor layer, a portion of the insulated gate field effect transistor has a low concentration drain (LDD) structure, and the low concentration drain region is extended to form the impurity region that has impurity concentration substantially identical to the low concentration drain region.

A method of manufacturing a solid state imaging device, comprising the steps of:

• forming a first buried layer of one conductivity type in an interior of a seventh semiconductor layer of opposite conductivity type by introducing one conductivity type impurity into the seventh semiconductor layer by using a first mask;
• forming a first well region of opposite conductivity type on a surface layer of the seventh semiconductor layer and over the first buried layer by introducing opposite conductivity type impurity into the seventh semiconductor layer by using the first mask;
• forming a one conductivity type region to be connected to the first buried layer and to contain the first well region by introducing one conductivity type impurity into the surface layer of the seventh semiconductor layer;
• forming a second buried layer of opposite conductivity type, that has higher impurity concentration than the seventh semiconductor layer, under the one conductivity type region by introducing opposite conductivity type impurity in an interior of the seventh semiconductor layer by using a second mask;
• forming a second well region of opposite conductivity type, that is connected to the first well region, by introducing opposite conductivity type impurity on a surface layer of the one conductivity type region and over the second buried layer by using the second mask;
• forming a channel doped layer of one conductivity type by introducing one conductivity type impurity on a surface layer of the second well region by using the second mask;
• forming a high concentration buried layer of opposite conductivity type, that has higher impurity concentration than the second well region, in an interior of the second well region under the channel doped layer by introducing opposite conductivity type impurity in an interior of the second well region by using a third mask;
• forming a gate insulating film on the seventh semiconductor layer by a thermal oxidation;
• forming a gate electrode on the gate insulating film to cover the high concentration buried layer and to bring the high concentration buried layer close to a source region side;
• forming an impurity region of one conductivity type on a surface layer of the first well region at a same time of forming a source region and a drain region of one conductivity type on a surface layer of the second well region on both sides of the gate electrode by introducing one conductivity type impurity on a surface layer of the seventh semiconductor layer;
• forming sidewalls on side surfaces of the gate electrode;
• and
• forming a resist film to cover a part of the impurity region acting as a light receiving portion, and then forming a contact layer that comes into contact with the drain region and has higher concentration than the drain region by introducing one conductivity impurity by using the gate electrode, the sidewalls, and the resist film as a mask.

A solid state imaging device manufacturing method comprising the steps of:

• forming a first well region of opposite conductivity type on a surface layer of one conductivity type region by introducing an opposite conductivity type impurity into the one conductivity type region of a surface layer of a semiconductor substrate;
• forming a second well region of opposite conductivity type connected to the first well region by introducing the opposite conductivity type impurity into a surface layer of the one conductivity type region;
• forming a channel doped layer of one conductivity type by introducing a one conductivity type impurity into a surface layer of the second well region;
• forming a high concentration buried layer of opposite conductivity type, that has an impurity concentration higher than the second well region, in an inside of the second well region under the channel doped layer by introducing the opposite conductivity type impurity into an inside of the second well region;
• forming a gate insulating film by thermally oxidizing a surface of the semiconductor substrate;
• forming a gate electrode on the gate insulating film to cover the high concentration buried layer and to bring the high concentration buried layer close to a source region side;
• forming one conductivity type source/drain regions on a surface layer of the second well region on both sides of the gate electrode and simultaneously forming a one conductivity type impurity region on a surface layer of the first well region, by introducing the one conductivity type impurity into a surface of the semiconductor substrate;
• and
• forming a resist film to cover a part of the impurity region acting as a light receiving portion, and then forming a high concentration contact layer, that comes in contact with the drain region and has a concentration higher than the drain region, by introducing the one conductivity type impurity while using the gate electrode and the resist film as a mask.