Low voltage transient voltage suppressor and method of making
AssigneeSemiconductor Components Industries, LLC
InventorsFrancine Y. Robb, Jeffrey Pearse, David M. Heminger, Stephen P. Robb
Life of this patent
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Abstract
A method of providing a Transient Voltage Suppression (TVS) device is described utilizing a Metal Oxide Semiconductor (MOS) structure and an Insulated Gate Bipolar Transistor (IGBT) structure. The MOS based TVS devices offer reduced leakage current with reduced clamp voltages between 0.5 and 5 volts. Trench MOS based TVS device (72) provides an enhanced gain operation, while device (88) provides a top side drain contact. The high gain MOS based TVS devices provide increased control over clamp voltage variation.
Claims31
A method of using a transient voltage suppression device, comprising:
- electrically coupling gate and drain terminals of a metal oxide semiconductor device;
- clamping a forward voltage applied across the transient voltage suppression device to be substantially equal to a threshold potential of the metal oxide semiconductor device;
- and
- clamping a reverse voltage applied across the transient voltage suppression device to be substantially equal to a barrier potential of the metal oxide semiconductor device.
A method of forming a transient voltage suppression device, comprising:
- electrically coupling gate and collector terminals of an insulated gate bipolar transistor device;
- clamping a forward voltage applied across the transient voltage suppression device to be substantially equal to a threshold potential of the insulated gate bipolar transistor device;
- and
- clamping a reverse voltage applied across the transient voltage suppression device to be substantially equal to a barrier potential of the insulated gate bipolar transistor device.
A method of using a transient voltage suppression device, comprising:
- electrically coupling gate and drain terminals of first and second metal oxide semiconductor devices;
- clamping a forward voltage applied across the transient voltage suppression device to be substantially equal to a first threshold potential of the first metal oxide semiconductor device;
- and
- clamping a reverse voltage applied across the transient voltage suppression device to be substantially equal to a second threshold potential of the second metal oxide semiconductor device.
A metal oxide semiconductor device used as a transient voltage suppressor, the transient voltage suppressor comprising:
- a semiconductor substrate having first and second surfaces;
- a body region of a first conductivity type formed in the first surface of the semiconductor substrate having first and second surfaces;
- a drain region of a second conductivity type formed in the second surface of the semiconductor substrate;
- and
- a trench gate region formed in the first surface of the semiconductor substrate.
An insulated gate bipolar transistor device used as a transient voltage suppressor, the transient voltage suppressor comprising:
- a semiconductor substrate having first and second surfaces;
- a body region of a first conductivity type formed in the first surface of the semiconductor substrate having first and second surfaces;
- a collector region of the first conductivity type formed in the second surface of the semiconductor substrate;
- and
- a trench gate region formed in the first surface of the semiconductor substrate.
A protection circuit, comprising:
- a utilization circuit (2) having an input coupled to receive an input signal at a first node;
- and
- a protection circuit coupled to the first node to substantially limit the input signal to a first level, the protection circuit including
- a transistor having a first conductor coupled to a control terminal of the transistor at the first node.
A protection circuit, comprising:
- a utilization circuit (2) having an input coupled to receive an input signal at first and second nodes;
- and
- a protection circuit (41) coupled to the first and second nodes to substantially limit the input signal between first and second levels, the protection circuit including,
- (a) a first transistor having a first conductor coupled to the first node;
- and
- (b) a second transistor having a first conductor coupled to the second node.
Dependencies are inferred from the claim text.